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参数资料
| 型号： | W19B324MBB9G |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封装： | TFBGA-48 |
| 文件页数： | 5/52页 |
| 文件大小： | 1955K |
| 代理商： | W19B324MBB9G |
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W19B32XMT/B
Publication Release Date: March 23, 2004
- 13 -
Revision A2
sequence contains the unlock bypass program command, A0h; the second cycle contains the
program address and data. In the same manner, additional data is programmed. This mode dispenses
with the initial two unlock cycles which required in the standard program command sequence,
resulting in faster total programming time.
All through the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset
commands are valid. The system must issue the two-cycle unlock bypass reset command sequence
to exit the unlock bypass mode. The first cycle must contain the bank address and the data 90h. The
second cycle need to contain the data 00h. Then, the bank returns to the read mode.
The device offers accelerated program operations by the #WP/ACC pin. When the VHH is set at the
#WP/ACC pin, the device automatically enters into the Unlock Bypass mode. Then, the two-cycle
Unlock Bypass program command sequence may be written. To accelerate the operation, the device
must use the higher voltage on the #WP/ACC pin. Please note that the #WP/ACC pin must not be at
VHH in any operation other than accelerated programming; otherwise the device may be damaged. In
addition, the #WP/ACC pin must not be left floating or unconnected; otherwise the device inconsistent
behavior may occur.
6.2.7 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation. Writing two unlock cycles initiates the chip erase command
sequence, which is followed by a set-up command. After chip erase command, two additional unlock
write cycles are then followed, which in turn invokes the Embedded Erase algorithm. The system
preprogram is not required prior to erase. Before electrical erase, the Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern. Any controls or
timings during these operations is not required in system.
As the Embedded Erase algorithm is complete, the bank returns to the read mode and addresses are
no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/#BY. Please refer to the Write Operation Status section for information on these status
bits.
Any commands written during the chip erase operation will be ignored. However, a hardware reset
shall terminate the erase operation immediately. If this happens, to ensure data integrity, the chip
erase command sequence should be reinitiated when that bank has returned to reading array data.
6.2.8 Sector Erase Command Sequence
Sector erase is a six-bus cycle operation. Writing two unlock cycles initiates the sector erase
command sequence, which is followed by a set-up command. Two additional unlock cycles are
written, and are then followed by the address of the sector to be erased, and the sector erase
command.
The device does not require the system to preprogram before erase. Before electrical erase, the
Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data
pattern. Any controls or timings during these operations is not required in system.
A sector erase time-out of 50
S occurs after the command sequence is written. Additional sector
addresses and sector erase commands may be written during the time-out period. Loading the sector
erase buffer may be done in any sequence, and the number of sectors may be from one sector to all
sectors. The time between these additional cycles must be less than 50
s; otherwise, erasure may
begin. Any sector erase address and command following the exceeded time-out may or may not be
accepted. To ensure all commands are accepted, processor interrupts be disabled during this time is
recommended. The interrupts can be re-enabled after the last Sector Erase command is written. Any
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| W1A | 功能描述:ENCLOSURE 7.25X4.5 GREY RoHS:是 类别:盒，外壳，支架 >> 箱 系列:工具 产品目录绘图:SR Series Standard 特色产品:Customize Your Enclosure 标准包装:1 系列:S 容器 - 类型:盒 尺寸/尺寸:3.600" L x 2.250" W（91.44mm x 57.15mm） 高度:1.500"（38.10mm） 面积 (L x W):8.10"（52.3cm） 设计:手持，分叉式双侧 材质:塑料 - ABS 颜色:杏黄 厚度:0.100"（2.54mm） 特点:PCB 支座 额定值:IP40，NEMA 1 材料可燃性额定值:UL94 HB 装运信息:从 Digi-Key 运送 重量:0.137 磅（62.14g） 相关产品:SR6005-ND - SCREW NO.4X 3/8 H/L PANSRPS-11-ND - GASKET 3.63 X 2.27 INCHSR52-ND - BOX RUBBER FEET FOR "A" SERIESSR410-ND - PC BOARD COPPER CLADSR310-ND - PC BOARD .1" STD HORIZ GRIDSR50-ND - RUBBER FEET (1XX,2XX) 其它名称:111-I ALMOND111-IA111-IALMONDSR111-IA |
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