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参数资料
| 型号： | W208D |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 3/14页 |
| 文件大小： | 169K |
| 代理商： | W208D |
W208D
PRELIMINARY
Document #: 38-07228 Rev. *A
Page 3 of 14
Overview
The W208D is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel
architec-
ture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
REF/SEL133 is a dual-purpose l/O pin. Upon power-up the pin
acts as a logic input. If the pin is strapped to a HIGH state
externally, CPU clock outputs will run at 133 MHz. If it is
strapped LOW, CPU clock outputs will be determined by the
status of SEL0:1 input pins. An external 10-k
strapping resis-
tor should be used.
Figure 1
shows a suggested method for
strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below tar-
get but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be pro-
duced from the CPU clock outputs when the outputs are
enabled.
Pin Selectable Functions
Table 1
outlines the device functions selectable through
SEL133 and SEL0:1. Specific outputs available at each pin are
detailed in
Table 2
below. The SEL0 pin requires a 220
pull-up resistor to 3.3V for the W208D to sense the maximum
host bus frequency of the processor and configure itself ac-
cordingly.
Notes:
2.
3.
4.
5.
6.
7.
Provided for board-level
“
bed of nails
”
testing.
“
Normal
”
mode of operation.
TCLK is a test clock overdriven on the XTAL_IN input during test mode.
Required for DC output impedance verification.
Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Output
Low
Q
D
W208D
V
DD
Clock Load
10 k
Output
(Load Option 1)
10k
(Load Option 0)
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Table 2. CK Whitney Truth Table
SEL133
SEL1
X
0
X
0
0
1
0
1
1
1
1
1
SEL0
0
1
0
1
0
1
CPU
Hi-Z
TCLK/4
66 MHz
100 MHz
SDRAM
Hi-Z
TCLK/4
100 MHz
100 MHz
3V66
Hi-Z
TCLK/6
66 MHz
66 MHz
PCI
Hi-Z
48MHz
Hi-Z
TCLK/2
48 MHz
48 MHz
REF
Hi-Z
TCLK
APIC
Hi-Z
TCLK/12
33 MHz
33 MHz
Notes
2
4, 5
3, 6, 7
3, 6, 7
TCLK/12
33 MHz
33 MHz
14.318 MHz
14.318 MHz
Reserved
133 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
3, 6, 7
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