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参数资料
| 型号： | W219B |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | XO, clock |
| 英文描述： | Frequency Generator for Integrated Core Logic with 133-MHz FSB |
| 中文描述： | OTHER CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, MO-118AA, SSOP-48 |
| 文件页数： | 2/15页 |
| 文件大小： | 175K |
| 代理商： | W219B |
W219B
PRELIMINARY
Document #: 38-07220 Rev. *A
Page 2 of 15
I
Pin Definitions
Pin Name
REF2x/FS3
Pin No.
1
Pin
Type
I/O
Pin Description
Reference Clock with 2x Drive/Frequency Select 3:
3.3V 14.318-MHz clock out-
put. This pin also serves as the select strap to determine device operating frequency
as described in
Table 1
.
Crystal Input:
This pin has dual functions. It can be used as an external 14.318-
MHz crystal connection or as an external reference frequency input.
Crystal Output:
An input connection for an external 14.318-MHz crystal connec-
tion. If using an external reference, this pin must be left unconnected.
PCI Clock 0/Frequency Selection 0:
3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1
.
PCI Clock 1/Frequency Selection 1:
3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1
.
PCI Clock 2/Frequency Selection 2:
3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1
.
PCI Clock 3 through 6:
3.3V 33-MHz PCI clock outputs. PCI0:6 can be individually
turned off via SMBus interface.
66-MHz Clock Output:
3.3V output clocks. The operating frequency is controlled
by FS0:4 (see
Table 1
).
48-MHz Clock Output
: 3.3V fixed 48-MHz, non-spread spectrum clock output.
48-MHz Clock Output/Frequency Selection 4:
3.3V fixed 48-MHz, non-spread
spectrum clock output. This pin also serves as the select strap to determine device
operating frequency as described in
Table 1
.
Clock Output for Super I/O:
This is the input clock for a Super I/O (SIO) device.
During power-up, it also serves as a selection strap. If it is sampled HIGH, the output
frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz.
Power Down Control:
LVTTL-compatible input that places the device in power-
down mode when held LOW.
CPU Clock Outputs:
Clock outputs for the host bus interface. Output frequencies
depending on the configuration of FS0:4. Voltage swing is set by VDDQ2.
SDRAM Clock Outputs:
3.3V outputs for SDRAM. The operating frequency is
controlled by FS0:4 (see
Table 1
).
X1
3
I
X2
4
I
PCI0/FS0
11
I/O
PCI1/FS1
12
I/O
PCI2/FS2
13
I/O
PCI3:6
15, 16, 18, 19
O
3V66_0:2
7, 8, 9
O
48MHz_0
48MHz_1/
FS4
21
22
O
I/O
SIO/
24_48#MHz
23
I/O
PWR_DWN#
29
I
CPU0:1
45, 44
O
SDRAM0:8
41, 40, 39, 37,
36, 35, 33, 32,
31
47
O
APIC
O
Synchronous APIC Clock Outputs:
Clock outputs running synchronous with the
PCI clock outputs. Voltage swing set by VDDQ2.
Data pin for SMBus circuitry.
Clock pin for SMBus circuitry.
3.3V Power Connection:
Power supply for SDRAM output buffers, PCI output buff-
ers, reference output buffers and 48-MHz output buffers. Connect to 3.3V.
2.5V Power Connection:
Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
Ground Connections:
Connect all ground pins to the common system ground
plane.
SDATA
SCLK
VDDQ3
25
28
I/O
I
P
2, 6, 17, 24, 27,
34, 42
46, 48
VDDQ2
P
GND
5, 10, 14, 20, 26,
30, 38, 43,
G
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