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参数资料
| 型号： | W245-30 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 6/12页 |
| 文件大小： | 108K |
| 代理商： | W245-30 |
W245-30
Document #: 38-07229 Rev. *B
Page 6 of 12
Serial Data Interface
The W245-30 features a two-pin, serial data interface that can
be used to configure internal register settings that control par-
ticular device functions. Upon power-up, the W245-30 initial-
izes with default register settings, therefore the use of this se-
rial data interface is optional. The serial interface is write-only
(to the clock chip) and is the dedicated function of device pins
SDATA and SCLOCK. In motherboard applications, SDATA
and SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power manage-
ment functions.
Table 3
summarizes the control functions of
the serial data interface.
Operation
Data is written to the W245-30 in eleven bytes of eight bits
each. Bytes are written in the order shown in
Table 4
.
Table 4. Byte Writing Sequence
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis-
abled outputs are actively held low.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock out-
puts to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change un-
der normal system operation.
Spread Spectrum En-
abling
Enables or disables spread spectrum clocking.
For EMI reduction.
Output Three-state
Puts clock output into a high impedance state.
Production PCB testing.
(Reserved)
Reserved function for future device revision or pro-
duction device testing.
No user application. Register bit must be writ-
ten as 0.
Byte Se-
quence
Byte Name
Bit Sequence
Byte Description
1
Slave Address
11010010
Commands the W245-30 to accept the bits in Data Bytes 0-6 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W245-30
is 11010010. Register setting will not be made if the Slave Address is
not correct (or is for an alternate slave receiver).
2
Command Code
Don
’
t Care
Unused by the W245-30, therefore bit values are ignored (don
’
t care).
This byte must be included in the data write sequence to maintain prop-
er byte allocation. The Command Code Byte is part of the standard
serial communication protocol and may be used when writing to anoth-
er addressed slave receiver on the serial data bus.
3
Byte Count
Don
’
t Care
Unused by the W245-30, therefore bit values are ignored (don
’
t care).
This byte must be included in the data write sequence to maintain prop-
er byte allocation. The Byte Count Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
4
Data Byte 0
Refer to
Table 5
The data bits in Data Bytes 0
–
7 set internal W245-30 registers that
control device operation. The data bits are only accepted when the
Address Byte bit sequence is 11010010, as noted above. For descrip-
tion of bit control functions, refer to
Table 3
, Data Byte Serial Configu-
ration Map.
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
11
Data Byte 7
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