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参数资料
| 型号： | W25X40AVSSIG |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 512K X 8 FLASH 2.7V PROM, PDSO8 |
| 封装： | 0.208 INCH, GREEN, PLASTIC, SOIC-8 |
| 文件页数： | 15/45页 |
| 文件大小： | 1344K |
| 代理商： | W25X40AVSSIG |
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W25X10A, W25X20A, W25X40A, W25X80A
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10.2.10 Page Program (02h)
The Page Program instruction allows up to 256 bytes of data to be programmed at previously erased
to all 1s (FFh) memory locations. A Write Enable instruction must be executed before the device will
accept the Page Program Instruction (Status Register bit WEL must equal 1). The instruction is
initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address
(A23-A0) and at least one data byte, into the DIO pin. The /CS pin must be held low for the entire
length of the instruction while data is being sent to the device.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address
bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the
remaining page length, the addressing will wrap to the beginning of the page. In some cases, less
than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the
same page. One condition to perform a partial page program is that the number of clocks can not
exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will
wrap to the beginning of the page and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS
is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See
AC Characteristics). While the Page Program cycle is in progress, the Read Status Register
instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during
the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit
in the Status Register is cleared to 0. The Page Program instruction will not be executed if the
addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register
Memory Protection table).
Figure 11. Page Program Instruction Sequence Diagram
相关PDF资料 |
PDF描述 |
|---|---|
| W25X80AVDAIZ | 1M X 8 FLASH 2.7V PROM, PDIP8 |
| W25X80ALSSIG | 1M X 8 FLASH 2.7V PROM, PDSO8 |
| W25X40ALDAIZ | 512K X 8 FLASH 2.7V PROM, PDIP8 |
| W25X10ALSNIG | 128K X 8 FLASH 2.7V PROM, PDSO8 |
| W27C257P-12 | 32K X 8 EEPROM 12V, 120 ns, PQCC32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W25X40AVZPIG | 功能描述:IC FLASH 16MBIT 100MHZ 8WSON RoHS:是 类别:集成电路 (IC) >> 存储器 系列:SpiFlash® 产品变化通告:Product Discontinuation 26/Apr/2010 标准包装:136 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步，DDR II 存储容量:18M（1M x 18） 速度:200MHz 接口:并联 电源电压:1.7 V ~ 1.9 V 工作温度:0°C ~ 70°C 封装/外壳:165-TBGA 供应商设备封装:165-CABGA（13x15） 包装:托盘 其它名称:71P71804S200BQ |
| W25X40BL | 制造商:WINBOND 制造商全称:Winbond 功能描述:1M-BIT, 2M-BIT AND 4M-BIT 2.5V SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI |
| W25X40BLDAIG | 制造商:WINBOND 制造商全称:Winbond 功能描述:1M-BIT, 2M-BIT AND 4M-BIT 2.5V SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI |
| W25X40BLSNIG | 制造商:WINBOND 制造商全称:Winbond 功能描述:1M-BIT, 2M-BIT AND 4M-BIT 2.5V SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI |
| W25X40BLSSIG | 制造商:WINBOND 制造商全称:Winbond 功能描述:1M-BIT, 2M-BIT AND 4M-BIT 2.5V SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI |
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