Preliminary W27LE520
Publication Release Date: June 2000
- 7 -
Revision A1
DC PROGRAMMING CHARACTERISTICS
(VDD = 6.5V
±0.25V, TA = 25° C ±5° C)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Input Load Current
ILI
VIN = VIL or VIH
-10
-
10
A
VDD Program Current
ICP
ALE = VIH,
OE /VPP = VPP
-
30
mA
VPP Program Current
IPP
ALE = VIH,
OE /VPP = VPP
-
30
mA
Input Low Voltage
VIL
-
-0.3
-
0.8
V
Input High Voltage
VIH
-
2.4
-
VDD +0.5
V
Output Low Voltage (Verify)
VOL
IOL = 2.1 mA
-
0.45
V
Output High Voltage (Verify)
VOH
IOH = -0.4 mA
2.4
-
V
A9 Silicon I.D. Voltage
VHH
VDD = 5V
±10%
11.5
12.0
12.5
V
VPP Program Voltage
VPP
-
12.75
13.0
13.25
V
VDD Supply Voltage (Program)
VDP
-
6.25
6.5
6.75
V
AC PROGRAMMING/ERASE CHARACTERISTICS
(VDD = 6.5V
±0.25V, TA = 25° C ±5° C)
PARAMETER
SYM.
LIMITS
UNIT
MIN.
TYP.
MAX.
OE /VPP Pulse Rise Time
TPRT
50
-
nS
Address Latch Enable Width
TALE
500
-
nS
ALE Program Pulse Width
TPPW
47.5
50
52.5
S
ALE Erase Pulse Width
TEPW
95
100
105
mS
ALE Erase Pulse Width 1
TEPW1
47.5
50
52.5
S
ALE Erase Pulse Width 2
TEPW2
95
100
105
mS
Latched Address Setup Time
TLAS
100
-
nS
Latched Address Hold Time
TLAH
100
-
nS
Address Setup Time
TAS
2.0
-
S
Address Hold Time
TAH
0
-
S
OE /VPP Setup Time
TOES
2.0
-
S
OE /VPP Hold Time
TOEH
2.0
-
S
Data Setup Time
TDS
2.0
-
S
Data Hold Time
TDH
2.0
-
S
Data Valid from OE /VPP Low during Erase Verify
TEOE
-
150
nS
Data Valid from OE /VPP Low during Program Verify
TPOE
-
150
nS
OE /VPP High to Output High Z
TDFP
0
-
130
nS
OE /VPP High Voltage Delay After ALE Low
TVS
2.0
-
S
OE /VPP Recovery Time
TVR
2.0
-
S
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.