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参数资料
| 型号： | W28J800TT90C |
| 元件分类： | EEPROM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件页数： | 4/51页 |
| 文件大小： | 1468K |
| 代理商： | W28J800TT90C |
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W28J800B/T
3. PRODUCT OVERVIEW
The product is a high-performance 8M-bit Boot Block Flash memory organized as 512k-word of 16
bits or 1M-byte of 8 bits. The 512k-word/1M-byte of data is arranged in two 4k-word/8k-byte boot
blocks, six 4k-word/8k-byte parameter blocks and fifteen 32k-word/64k-byte main blocks which are
individually erasable, lockable and unlockable in-system. The memory map is shown in Figure 3.
The dedicated V
PP
pin gives complete data protection when V
PP
≤
V
PPLK
.
A Command User Interface (CUI) serves as the interface between the system processor and internal
operation of the device. A valid command sequence written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for
block erase, full chip erase, word/byte write and lock-bit configuration operations.
A block erase operation erases one of the device’s 32k-word/64k-byte blocks typically within 1.2S (3V
V
DD
, 3V V
PP
), 4k-word/8k-byte blocks typically within 0.6s (3V V
DD
, 3V V
PP
) independent of other
blocks. Each block can be independently erased minimum 100,000 times. Block erase suspend mode
allows system software to suspend block erase to read or write data from any other block.
Writing memory data is performed in word/byte increments of the device’s 32k-word blocks typically
within 33
μ
S (3V V
DD
, 3V V
PP
), 64k-byte blocks typically within 31
μ
S (3V V
DD
, 3V V
PP
), 4k-word
blocks typically within 36
μ
S (3V V
DD
, 3V V
PP
), 8k-byte blocks typically within 32
μ
S (3V V
DD
, 3V V
PP
).
Word/byte write suspend mode enables the system to read data or execute code from any other flash
memory array location.
Individual block locking uses a combination of bits, thirty-nine block lock-bits, a permanent lock-bit and
#WP pin, to lock and unlock blocks. Block lock-bits gate block erase, full chip erase and word/byte
write operations, while the permanent lock-bit gates block lock-bit modification and locked block
alternation. Lock-bit configuration operations (Set Block Lock-Bit, Set Permanent Lock-Bit and Clear
Block Lock-Bits commands) set and cleared lock-bits.
The status register indicates when the WSM’s block erase, full chip erase, word/byte write or lock-bit
configuration operation is finished.
The RY/#BY output gives an additional indicator of WSM activity by providing both a hardware signal
of status (versus software polling) and status masking (interrupt masking for background block erase,
for example). Status polling using RY/#BY minimizes both CPU overhead and system power
consumption. When low, RY/#BY indicates that the WSM is performing a block erase, full chip erase,
word/byte write or lock-bit configuration. RY/#BY-high Z indicates that the WSM is ready for a new
command, block erase is suspended (and word/byte write is inactive), word/byte write is suspended,
or the device is in reset mode.
The access time is 90 nS (t
AVQV
) over the operating temperature range and V
DD
supply voltage range
of 2.7V to 3.6V.
The Automatic Power Savings (APS) feature substantially reduces active current when the device is in
static mode (addresses not switching). In APS mode, the typical I
CCR
current is 2
μ
A (CMOS) at 3.0V
V
DD
.
When #CE and #RESET pins are at V
DD
, the I
CC
CMOS standby mode is enabled. When the #RESET
pin is at V
SS
, reset mode is enabled which minimizes power consumption and provides write
protection. A reset time (t
PHQV
) is required from #RESET switching high until outputs are valid.
Likewise, the device has a wake time (t
PHEL
) from #RESET-high until writes to the CUI are recognized.
With #RESET at V
SS
, the WSM is reset and the status register is cleared.
- 4 -
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