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参数资料
| 型号： | W3EG6432S403D3 |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM MODULE, 0.7 ns, DMA184 |
| 封装： | ROHS COMPLIANT, DIMM-184 |
| 文件页数： | 11/13页 |
| 文件大小： | 405K |
| 代理商： | W3EG6432S403D3 |
White Electronic Designs
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
December 2006
Rev. 7
PRELIMINARY
W3EG6432S-D3
-JD3
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
AC CHARACTERISTICS
403
335
262
263/265
202
PARAMETER
SYMBOL MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX UNITS NOTES
Access window of DQs from CK/CK#
tAC
-0.7
+0.7
-0.7
+0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
26
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
26
Clock cycle time
CL = 3
tCK (3)
5
7.5
ns
40, 45
CL = 2.5
tCK (2.5)
6
13
6
13
7.5
13
7.5
13
7.5
13
ns
40, 45
CL = 2
tCK (2)
7.5
13
7.5
13
7.5/10
13
7.5/10
13
7.5/10
13
ns
40, 45
DQ and DM input hold time relative to DQS
tDH
0.4
0.45
0.5
ns
23, 27
DQ and DM input setup time relative to DQS
tDS
0.4
0.45
0.5
ns
23, 27
DQ and DM input pulse width (for each input)
tDIPW
1.75
ns
27
Access window of DQS from CK/CK#
tDQSCK
-0.60 +0.60 -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per
access
tDQSQ
0.40
0.45
0.5
ns
22, 23
Write command to rst DQS latching transition
tDQSS
0.72
1.28
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising - setup time
tDSS
0.2
tCK
DQS falling edge from CK rising - hold time
tDSH
0.2
tCK
Half clock period
tHP
tCH,tCL
ns
30
Data-out high-impedance window from CK/CK#
tHZ
+0.70
+0.75
ns
16, 36
Data-out low-impedance window from CK/CK#
tLZ
-0.70
-0.75
ns
16, 36
Address and control input hold time (fast slew rate)
tIHF
0.6
0.75
0.90
.90
ns
12
Address and control input setup time (fast slew rate)
tISF
0.6
0.75
0.90
.90
ns
12
Address and control input hold time (slow slew rate)
tIHS
0.6
0.80
1
ns
12
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PDF描述 |
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| W3EG6432S265JD3 | 32M X 64 DDR DRAM MODULE, 0.75 ns, DMA184 |
| W3EG6433S262AD4 | 32M X 64 DDR DRAM MODULE, 0.75 ns, DMA200 |
| W3EG6433S335BD4 | 32M X 64 DDR DRAM MODULE, 0.7 ns, DMA200 |
| W3EG6433S335JD3 | 32M X 64 DDR DRAM MODULE, 0.7 ns, DMA184 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W3EG6432S403JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6432S-D3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6432S-D4 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6433S202AD4 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| W3EG6433S202BD4 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
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