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参数资料
| 型号： | W3EG6433S262AD4 |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封装： | SODIMM-200 |
| 文件页数： | 9/13页 |
| 文件大小： | 321K |
| 代理商： | W3EG6433S262AD4 |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6433S-AD4
-BD4
May 2005
Rev. 1
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specications without notice.
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V
DDR333@CL=2.5 DDR266@CL=2, 2.5
DDR200@CL=2
Parameter
Symbol Conditions
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge;
tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS
inputs changing once per clock cycle; Address
and control inputs changing once every two
cycles.
1275
1276
1235
mA
Operating Current
IDD1
One device bank; Active-Read-Precharge;
Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN); Iout =
0mA; Address and control inputs changing
once per clock cycle.
1635
1555
1435
mA
Precharge Power-Down
Standby Current
IDD2P
All device banks idle; Power- down mode;
tCK=tCK(MIN); CKE=(low)
32
mA
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK=tCK(MIN); CKE = high; Address and other
control inputs changing once per clock cycle.
Vin = Vref for DQ, DQS and DM.
675
635
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down mode;
tCK(MIN); CKE=(low)
240
200
240
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS(MAX);
tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle.
755
675
mA
Operating Current
IDD4R
Burst = 2; Reads; Continous burst; One
device bank active;Address and control inputs
changing once per clock cycle; tCK=tCK(MIN);
Iout = 0mA.
1675
1475
mA
Operating Current
IDD4W
Burst = 2; Writes; Continous burst; One
device bank active; Address and control inputs
changing once per clock cycle; tCK=tCK(MIN);
DQ,DM and DQS inputs changing twice per
clock cycle.
1675
1475
mA
Auto Refresh Current
IDD5
tRC=tRC(MIN)
2315
2155
2235
mA
Self Refresh Current
IDD6
CKE
≤ 0.2V
307
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK(MIN);
Address and control inputs change only
during Active Read or Write commands.
3555
3075
3195
mA
* For DDR333 consult factory
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相关代理商/技术参数 |
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|---|---|
| W3EG6433S262BD4 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| W3EG6433S262D3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| W3EG6433S263D3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| W3EG6433S263JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| W3EG6433S265AD4 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
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