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参数资料
| 型号： | W3EG6433S335JD3 |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM MODULE, 0.7 ns, DMA184 |
| 封装： | DIMM-184 |
| 文件页数： | 11/12页 |
| 文件大小： | 262K |
| 代理商： | W3EG6433S335JD3 |
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3EG6433S-D3
-JD3
November 2005
Rev. 2
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
AC Characteristics
335
(DDR333@CL=2.5)
262
(DDR266@CL=2.0)
263
(DDR266@CL=2.0)
265
(DDR266@CL=2.5)
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Units
Notes
Output Slew Rate (x4,x8)
tSL(O)
1.0
4.5
1.0
4.5
1.0
4.5
1.0
4.5
V/ns
Output Slew Rate Matching Ratio (rise
to fall)
tSLMR
0.67
1.5
0.67
1.5
0.67
1.5
0.67
1.5
ns
Mode register set cycle time
tMRD
12
15
ns
j, k
DQ & DM setup time to DQS
tDS
0.5
ns
j, k
DQ & DM hold time to DQS
tDH
0.45
0.5
ns
8
Control & Address input pulse width
tIPW
2.2
ns
8
DQ & DM input pulse width
tDIPW
1.75
ns
Power down exit time
tRDEX
6
7.5
ns
Exit self refresh to non-Read command
tXSRD
75
ns
Exit self refresh to read command
tXSRD
200
tCK
Refreash interval time
tREFI
15.6
us
4
Output DQS valid window
tQH
tHP-tQHS
-tHP-tQHS
ns
11
Clock half period
tQH
tCLmin or
tchmin
-
tCLmin or
tchmin
-
tCLmin or
tchmin
-
tCLmin or
tchmin
ns
10, 11
Data hold skew factor
tQHS
0.55
0.75
ns
11
DQS write postamble time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
2
Active to Read with Auto precharge
command
tRAP
18
20
Autoprecharge write recovery &
Precharge time
tXSNR
tWR/tCK
+
tRP/tCK)
tWR/tCK
+
tRP/tCK)
tWR/tCK
+
tRP/tCK)
tWR/tCK
+
tRP/tCK)
tCK
13
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相关代理商/技术参数 |
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| W3EG6433S-AD4 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
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