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参数资料
| 型号： | W3EG6464S265BD4 |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, DMA200 |
| 封装： | SO-DIMM-200 |
| 文件页数： | 5/9页 |
| 文件大小： | 77K |
| 代理商： | W3EG6464S265BD4 |
W3EG6464S-AD4
-BD4
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
March 2004
Rev. 1
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C TA 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Parameter
Symbol Conditions
DDR333
@CL=2.5
Max
DDR266
@CL=2
Max
DDR266
@CL=2.5
Max
DDR200
@CL=2
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge; tRC=tRC(MIN);
tCK=tCK(MIN); DQ,DM and DQS inputs changing once per
clock cycle; Address and control inputs changing once every
two cycles.
TBD
1595
mA
Operating Current
IDD1
One device bank; Active-Read-Precharge; Burst = 2;
tRC=tRC(MIN);tCK=tCK(MIN); Iout = 0mA; Address and control
inputs changing once per clock cycle.
TBD
1795
mA
Precharge Power-Down
Standby Current
IDD2P
All device banks idle; Power- down mode; tCK=tCK(MIN);
CKE=(low)
TBD
48
mA
Idle Standby Current
IDD2F
CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high;
Address and other control inputs changing once per clock
cycle. Vin = Vref for DQ, DQS and DM.
TBD
675
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down mode; tCK(MIN);
CKE=(low)
TBD
400
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One device bank; Active-Precharge;
tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.
TBD
1035
mA
Operating Current
IDD4R
Burst = 2; Reads; Continous burst; One device bank
active;Address and control inputs changing once per clock
cycle; tCK=tCK(MIN); Iout = 0mA.
TBD
2035
mA
Operating Current
IDD4W
Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per
clock cycle.
TBD
2275
mA
Auto Refresh Current
IDD5
tRC=tRC(MIN)
TBD
2755
mA
Self Refresh Current
IDD6
CKE 0.2V
TBD
315
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4) with auto precharge
with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs
change only during Active Read or Write commands.
TBD
4115
mA
* For DDR333 consult factory
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相关代理商/技术参数 |
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|---|---|
| W3EG6464S265D3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM UNBUFFERED |
| W3EG6464S265JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM UNBUFFERED |
| W3EG6464S335AD4 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM UNBUFFERED w/PLL |
| W3EG6464S335BD4 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM UNBUFFERED w/PLL |
| W3EG6464S-AD4 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM UNBUFFERED w/PLL |
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