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参数资料
| 型号： | W3EG64M64ETSU403D4IMG |
| 英文描述： | 512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| 中文描述： | 512MB的- 64Mx64 DDR SDRAM，可缓冲，SO - DIMM插槽 |
| 文件页数： | 6/12页 |
| 文件大小： | 190K |
| 代理商： | W3EG64M64ETSU403D4IMG |
WV3EG64M64ETSU-D4
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
I
CC
SPECIFICATIONS AND CONDITIONS
0°C ≤ T
A
≤ +70°C DDR400: V
CC
= V
CCQ
= +2.6V ±0.1V
Symbol
Parameter/Condition
Max
Max
Units
DDR400
@CL=3
DDR333
@CL=2.5
I
CC0
OPERATING CURRENT: One device bank; Active-Precharge; t
= t
(MIN); t
= t
(MIN);
DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing
once every two clock cycles
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; t
= t
RC
(MIN);
t
CK
= t
CK
(MIN); I
OUT
= 0mA; Address and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down
mode; t
CK
= t
CK
(MIN); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; t
= t
(MIN); CKE =
HIGH; Address and other control inputs changing once per clock cycle. V
IN
= V
REF
for DQ, DQS,
and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode;
t
CK
= t
CK
(MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; t
= t
RAS
(MAX); t
= t
(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address
and control inputs changing once per clock cycle; t
CK
= t
CK
(MIN); I
OUT
= 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address
and control inputs changing once per clock cycle; t
CK
= t
CK
(MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
AUTO REFRESH BURST CURRENT:
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge,
t
= minimum t
allowed; t
= t
CK
(MIN); Address and control inputs change only during
Active READ, or WRITE commands
960
840
mA
I
CC1
1,200
1,080
mA
I
CC2P
40
40
mA
I
CC2F
240
240
mA
I
CC3P
360
200
mA
I
CC3N
480
360
mA
I
CC4R
1,240
1,120
mA
I
CC4W
1,400
1,200
mA
I
CC5
I
CC6
t
REFC
= t
RFC
(MIN)
1,760
40
1,640
40
mA
mA
I
CC7
3,080
2,880
mA
Notes:
CC
parameters are based on
SAMSUNG
components. Other DRAM manufactures parameter may be different
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W3EG64M64ETSU403D4ISG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| W3EG64M64ETSU403D4MG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| W3EG64M64ETSU403D4SG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| W3EG72125S202AJD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72125S202D3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL |
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