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参数资料
| 型号： | W3EG72125S202AJD3 |
| 英文描述： | 1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| 中文描述： | 1GB的- 2x64Mx72 ECC的DDR SDRAM的注册瓦特/锁相环 |
| 文件页数： | 7/14页 |
| 文件大小： | 389K |
| 代理商： | W3EG72125S202AJD3 |
W3EG72125S-D3
-JD3
-AJD3
PRELIMINARY
November 2004
Rev. 2
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
I
DD1
: Operating Current : One Bank
1. Typical Case : V
CC
= 2.5V, T = 25°C
2. Worst Case : V
CC
= 2.7V, T = 10°C
3. Only one bank is accessed with t
RC
(min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. I
OUT
= 0mA
4. Timing Patterns :
DDR200 (100 MHz, CL = 2) : t
CK
= 10ns, CL2,
BL=4, t
RCD
= 2*t
CK
, t
RAS
= 5*t
CK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
DDR266 (133MHz, CL=2.5) : t
CK
= 7.5ns,
CL = 2.5, BL = 4, t
RCD
= 3*tCK, t
RC
= 9*t
CK
,
t
RAS
= 5*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR266 (133MHz, CL = 2) : t
CK
= 7.5ns,
CL = 2, BL = 4, t
RCD
= 3*t
CK
, t
RC
= 9*t
CK
,
t
RAS
= 5*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR333 (166MHz, CL = 2.5) : t
CK
= 6ns,
BL = 4, t
RCD
= 10*t
CK
, t
RAS
= 7*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
I
DD7A
: Operating Current: Four Banks
1. Typical Case : V
CC
= 2.5V, T = 25°C
2. Worst Case : V
CC
= 2.7V, T = 10°C
3. Four banks are being interleaved with t
RC
(min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. I
OUT
=0mA
4. Timing Patterns :
DDR200 (100 MHz, CL = 2) : t
CK
= 10ns, CL2,
BL = 4, t
RRD
= 2*t
CK
, t
RCD
= 3*t
CK
, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
DDR266 (133MHz, CL = 2.5) : t
CK
= 7.5ns,
CL = 2.5, BL = 4, t
RRD
= 3*t
CK
, t
RCD
= 3*t
CK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR266 (133MHz, CL = 2) : t
CK
= 7.5ns,
CL2 = 2, BL = 4, t
RRD
= 2*t
CK
, t
RCD
= 2*t
CK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR333 (166MHz, CL=2.5) : t
CK
=6ns,
BL=4, t
RRD
=3*t
CK
, t
RCD
=3*t
CK
, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DETAILED TEST CONDITIONS FOR DDR SDRAM I
DD1
& I
DD7A
Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W3EG72125S202D3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72125S202JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72125S262AJD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72125S262D3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72125S262JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL |
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