- 您现在的位置：买卖IC网 > PDF目录68454 > W3EG72129S202JD3M (WHITE ELECTRONIC DESIGNS CORP) 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 PDF资料下载
参数资料
| 型号： | W3EG72129S202JD3M |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封装： | DIMM-184 |
| 文件页数： | 8/12页 |
| 文件大小： | 171K |
| 代理商： | W3EG72129S202JD3M |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
October 2005
Rev. 3
W3EG72129S-JD3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C
≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
DDR400@
CL=3
Max
DDR333@
CL=2.5
Max
DDR266@
CL=2
Max
DDR266@
CL=2.5
Max
DDR200@
CL=2
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
4950
4140
mA
Operating Current
IDD1
One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
5490
4680
mA
Precharge Power-
Down Standby Current
IDD2P
All device banks idle; Power-down
mode; tCK=tCK (MIN); CKE=(low)
180
rnA
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. VIN = VREF for
DQ, DQS and DM.
1980
1620
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-
Down mode; tCK (MIN); CKE=(low)
1620
1260
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
2160
1800
mA
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; TCK= TCK (MIN); lOUT
= 0mA.
5580
4770
mA
Operating Current
IDD4W
Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
5670
4590
rnA
Auto Refresh Current
IDD5
tRC = tRC (MIN)
8370
7020
mA
Self Refresh Current
IDD6
CKE
≤ 0.2V
180
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
(MIN); tCK=tCK (MIN); Address and
control inputs change only during
Active Read or Write commands.
10260
9090
9000
mA
相关PDF资料 |
PDF描述 |
|---|---|
| W3EG72129S403JD3S | 128M X 72 DDR DRAM MODULE, 0.7 ns, DMA184 |
| W3EG72129S265JD3 | DDR DRAM MODULE, DMA184 |
| W3EG7217S265D3 | 16M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| W3EG7218S265BD4 | 16M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| W3EG72255S263AJD3SG | 256M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W3EG72129S262JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG72129S263JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG72129S265JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG72129S335JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG72129S403JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED w/PLL |
发布紧急采购，3分钟左右您将得到回复。