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参数资料
| 型号： | W3EG7218S265BD4 |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封装： | SODIMM-200 |
| 文件页数： | 12/13页 |
| 文件大小： | 179K |
| 代理商： | W3EG7218S265BD4 |
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
November 2004
Rev. 1
PRELIMINARY
W3EG7218S-AD4
-BD4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued)
AC CHARACTERISTICS
262
265/202
UNITS
NOTES
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
DQ-DQS hold, DQS to rst DQ to go non-valid, per access
tQH
tHP - tQHS
ns
22, 23
Data Hold Skew Factor
tQHS
0.75
ns
ACTIVE to PRECHARGE command
tRAS
40
120,000
40
120,000
ns
31, 48
ACTIVE to READ with Auto precharge command
tRAP
15
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
60
65
ns
AUTO REFRESH command period
tRFC
75
ns
43
ACTIVE to READ or WRITE delay
tRCD
15
20
ns
PRECHARGE command period
tRP
15
20
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
38
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
38
ACTIVE bank a to ACTIVE bank b command
tRRD
15
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time
tWPRES
0
ns
18, 19
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
17
Write recovery time
tWR
15
ns
Internal WRITE to READ command delay
tWTR
11
tCK
Data valid output window (DVW)
na
tQH - tDQSQ
ns
22
REFRESH to REFRESH command interval
tREFC
140.6
μs21
Average periodic refresh interval
tREFI
15.6
μs21
Terminating voltage delay to VDD
tVTD
00
ns
Exit SELF REFRESH to non-READ command
tXSNR
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
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相关代理商/技术参数 |
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| W3EG7218S-AD4 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
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