参数资料
型号: W3EG7232S262AD4-M
厂商: WHITE ELECTRONIC DESIGNS CORP
元件分类: DRAM
英文描述: 32M X 72 DDR DRAM MODULE, 0.75 ns, DMA200
封装: SO-DIMM-200
文件页数: 12/14页
文件大小: 308K
代理商: W3EG7232S262AD4-M
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7232S-AD4
-BD4
August 2005
Rev. 4
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
AC CHARACTERISTICS
SYMBOL
335
262
265
202
UNITS NOTES
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Access window of DQs from CK/CK#
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
-0.75
+0.75
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
26
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
26
Clock cycle time
CL = 2.5
tCK (2.5)
6
13
7.5
13
7.5
13
7.5
13
ns
39, 44
CL = 2
tCK (2)
7.5
13
7.5
13
7.5
13
10
13
ns
39, 44
DQ and DM input hold time relative to DQS
tDH
0.45
0.5
ns
23, 27
DQ and DM input setup time relative to DQS
tDS
0.45
0.5
ns
23, 27
DQ and DM input pulse width (for each input)
tDIPW
1.75
ns
27
Access window of DQS from CK/CK#
tDQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
-0.75
+0.75
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per
access
tDQSQ
0.45
0.5
0.6
ns
22, 23
Write command to rst DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising - setup time
tDSS
0.2
tCK
DQS falling edge from CK rising - hold time
tDSH
0.2
tCK
Half clock period
tHP
tCH, tCL
ns
30
Data-out high-impedance window from CK/CK#
tHZ
+0.7
+0.75
ns
16, 36
Data-out low-impedance window from CK/CK#
tLZ
-0.7
-0.75
ns
16, 36
Address and control input hold time (slow slew rate)
tIHS
0.80
0.90
1
1.1
ns
12
Address and control input setup time (slow slew rate)
tISS
0.80
0.90
1
1.1
ns
12
Address and Control input pulse width (for each input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
12
15
ns
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