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参数资料
| 型号： | W3HG64M64EEU403D4SG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.6 ns, DMA200 |
| 封装： | ROHS COMPLIANT, SODIMM-200 |
| 文件页数： | 7/12页 |
| 文件大小： | 207K |
| 代理商： | W3HG64M64EEU403D4SG |
W3HG64M64EEU-D4
October 2005
Rev. 0
ADVANCED
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
RECOMMENDED DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Units
Notes
Supply Voltage
VCC
1.7
1.9
V
-
I/O Reference Voltage
VREF
0.49 x VCC
0.51 x VCC
V1
I/O Termination Voltage (system)
VTT
VREF - 40
VREF + 40
mV
2
NOTE:
1. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed
±1percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of VREF (DC). This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF and must track variations in the DC level of VREF.
ABSOLUTE MAXIMUM DC CHARACTERISTICS
Symbol
Parameter
Min
Max
Units
VCC
VCC Supply Voltage Relative to VSS
-0.5
2.3
V
VIN, VOUT Voltage on any Pin Relative to VSS
-0.5
2.3
V
TSTG
Storage Temperature
-55
100
°C
TCASE
DDR2 SDRAM Device Operating Temperature*
0
85
°C
TOPR
Operating Temperature (Ambient)
0
65
°C
II
Input Leakage Current; Any input 0V ≤ VIN ≤ VCC;
VREF input 0V ≤ VIN ≤0.95V; (All other pins not under
test = 0V)
Command/Address,
RAS#, CAS#, WE# S#,
CKE
-40
40
μA
CK, CK#
-20
20
DM
-5
5
IOZ
Output Leakage Current; 0V ≤ VOUT ≤ VCCQ; DQs
and ODT are disabled
DQ, DQS, DQS#
-5
5
μA
IVREF
VREF Leakage Current; VREF = Valid VREF level
-16
16
μA
* TCASE species as the temperature at the top center of the memory devices.
CAPACITANCE
TA = 25°C, f = 1MHz, V = 1.8V
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
CIN1
TBD
pF
Input Capacitance (RAS#,CAS#,WE#)
CIN2
TBD
pF
Input Capacitance (CKE0)
CIN3
TBD
pF
Input Capacitance (CK0, CK0#)
CIN4
TBD
pF
Input Capacitance (S0#)
CIN5
TBD
pF
Input Capacitance (DQS0#-DQS17#)
CIN6
TBD
pF
Input Capacitance (BA0-BA1)
CIN7
TBD
pF
Data input/output Capacitance (DQ0-DQ63)
COUT
TBD
pF
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