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参数资料
| 型号： | W3HG64M64EEU534D4MG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.5 ns, DMA200 |
| 封装： | ROHS COMPLIANT, SODIMM-200 |
| 文件页数： | 11/12页 |
| 文件大小： | 207K |
| 代理商： | W3HG64M64EEU534D4MG |
W3HG64M64EEU-D4
October 2005
Rev. 0
ADVANCED
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
AC OPERATING CONDITIONS (continued)
≤TCASE≤+85°C; VCC = +1.8V ±0.1V
Self
Refresh
AC Characteristics
Symbol
806
665
534
403
Units
Notes
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
REFRESH to Active or Refresh to Refresh command interval tRFC (512MB)
TBD
105 70,000 150 70,000 105 70,000
14
Average periodic refresh interval
tXSNR
TBD
7.8
μs
14
Exit self refresh to non-READ command
tXSNR
TBD
tRFC
(MIN)
+ 10
tRFC
(MIN)
+ 10
tRFC
(MIN)
+ 10
ns
Exit self refresh to READ command
tXSRD
TBD
200
tCK
Exit self refresh timing reference
tISXR
TBD
tIS
ps
6, 30
ODT
ODT turn-on delay
tAOND
TBD
22222
tCK
ODT turn-on
tAOND
tAC (MIN)
tAC (MAX
+ 700)
tAC (MIN)
tAC (MAX
+ 1,000)
tAC (MIN)
tAC (MAX
+ 1,000)
ps
26
ODT turn-off delay
tAOFD
TBD
2.5
tCK
ODT turn-off
tAOF
TBD
tAC (MIN)
tAC (MAX
+ 600)
tAC (MIN)
tAC (MAX
+ 600)
tAC (MIN)
tAC (MAX
+ 600)
ps
27
ODT turn-on (power-down mode)
tAONPD
TBD
tAC (MIN)
+ 2,000
tAC
(MAX) +
1,000
tAC (MIN)
+ 2,000
tAC
(MAX) +
1,000
tAC (MIN)
+ 2,000
tAC
(MAX) +
1,000
ps
ODT turn-off (power-down mode)
tAOFPD
TBD
tAC (MIN)
+ 2,000
tAC
(MAX) +
1,000
tAC (MIN)
+ 2,000
tAC
(MAX) +
1,000
tAC (MIN)
+ 2,000
tAC
(MAX) +
1,000
ps
ODT to power-down entry latency
tANPD
TBD
333tCK
ODT power-down exit latency
tAXPD
TBD
888tCK
Power
Down
Exit active power-down to READ command, MR[bit12=0]
tXARD
TBD
222tCK
Exit active power-down to READ command, MR[bit12=1]
tXARDS
TBD
7 - AL
6 - AL
Exit precharge power-down to any non-READ command.
tXP
TBD
222tCK
CKE minimum high/low time
tCKE
TBD
333tCK
35
Note:
AC specication is based on
MICRON components. Other DRAM manufactures specications may be different.
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