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参数资料
| 型号： | W3HG64M72EEU806PD4GG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, DMA200 |
| 封装： | ROHS COMPLIANT, SO-CDIMM-200 |
| 文件页数： | 9/11页 |
| 文件大小： | 149K |
| 代理商： | W3HG64M72EEU806PD4GG |
W3HG64M72EEU-PD4
May 2007
Rev. 1
ADVANCED
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Clock
Clock cycle time
CL = 6
tCK (6)
TBD
ps
CL = 5
tCK (5)
TBD
3,000
8,000
3,750
8,000
5,000
8,000
ps
CL = 4
tCK (4)
TBD
3,750
8,000
3,750
8,000
5,000
8,000
ps
CL = 3
tCK (3)
TBD
5,000
8,000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Half clock period
tHP
TBD
MIN
(tCH,tCL)
MIN
(tCH,tCL)
MIN
(tCH,tCL)
ps
Clock jitter
tJIT
TBD
-125
125
-125
125
-125
125
ps
Data
DQ output access time from CK/CK#
tAC
TBD
-450
+450
-500
+500
-600
+600
ps
Data-out high-impedance window from
CK/CK#
tHZ
TBD
tAC(MAX)
ps
Data-out low-impedance window from
CK/CK#
tLZ
TBD
2x
tAC(MIN)
tAC(MAX)
2x
tAC(MIN)
tAC(MAX)
2x
tAC(MIN)
tAC(MAX)
ps
DQ and DM input setup time relative to
DQS
tDS
TBD
100
150
DQ and DM input hold time relative to DQS
tDH
TBD
175
225
275
DQ and DM input pulse width (for each
input)
tDIPW
TBD
0.35
tCK
Data hold skew factor
tQHS
TBD
340
400
450
ps
DQ - DQS hold, DQS to rst DQ to go
nonvalid, per access
tQH
TBD
tHP - tQHS
ps
Data valid output window (DVW)
tDVW
TBD
tQH - tDQSQ
ns
Data
Strobe
DQS input high pulse width
tDQSH
TBD
0.35
tCK
DQS input low pulse width
tDQSL
TBD
0.35
tCK
DQS output access time from CK/CK#
tDQSCK
TBD
-400
+400
-450
+450
-500
+500
ps
DQS falling edge to CK rising … setup time
tDSS
TBD
0.2
tCK
DQS falling edge from CK rising … hold
time
tDSH
TBD
0.2
tCK
DQS - DQ skew, DQS to last DQ valid, per
group, per access
tDQSQ
TBD
240
300
350
ps
DQS read preamble
tRPRE
TBD
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
TBD
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS write preamble setup time
tWPRES
TBD
000
p s
DQS write preamble
tWPRE
TBD
0.35
tCK
DQS write postamble
tWPST
TBD
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to rst DQS latching
transition
tDQSS
TBD
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
tCK
Address and control input pulse width for
each input
tIPW
TBD
0.6
tCK
Address and control input setup time
tIS
TBD
200
250
350
ps
Address and control input hold time
tIH
TBD
275
375
475
ps
Address and control input hold time
tCCD
TBD
222
tCK
* AC specication is based on
QIMONDA components. Other DRAM manufactures specication may be different.
Continued on next page
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