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参数资料
| 型号： | W49F002UT70BN |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 256K X 8 FLASH 5V PROM, 70 ns, PDSO32 |
| 封装： | 8 X 20 MM, TSOP-32 |
| 文件页数： | 27/30页 |
| 文件大小： | 0K |
| 代理商： | W49F002UT70BN |
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W49F002U
- 6 -
Byte 0 (A0 = VIL) represents the manufacturer
′s code (Winbond = DAh) and byte 1 (A0 = VIH) the
device identifier code (W49F002U = 0Bh,). All identifiers for manufacturer and device will exhibit odd
parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the
Auto-select, A1 must be VIL.
6.1.6 Reset Mode: Hardware Reset
The #RESET pin provides a hardware method of resetting the device to reading array data. When the
system drives the #RESET pin low for at least a period of tRP, the device immediately terminates any
operation in progress, tri-states all data output pins, and ignores all read/write attempts for the duration
of the #RESET pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the #RESET pulse. When #RESET is held at VIL, the device
enters the TTL standby mode; if #RESET is held at Vss, the device enters the CMOS standby mode.
The #RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
6.2 Data Protection
The W49F002U is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device
automatically resets the internal state machine in the Read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific
multi-bus cycle command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from VDD power-up and power-down transitions or system noise.
6.2.1 Low VDD Inhibit
To avoid initiation of a write cycle during VDD power-up and power-down, the W49F002U locks out
when VDD < 2.5V. The write and read operations are inhibited when VDD is less than 2.5V typical. The
W49F002U ignores all write and read operations until VDD > 2.5V. The user must ensure that the
control pins are in the correct logic state when VDD > 2.5V to prevent unintentional writes.
6.2.2 Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #OE, or #WE will not initiate a write cycle.
6.2.3 Logical Inhibit
Writing is inhibited by holding any one of #OE = VIL, #CE = VIH, or #WE = VIH. To initiate a write cycle
#CE and #WE must be a logical zero while #OE is a logical one.
6.2.4 Power-up Write and Read Inhibit
Power-up of the device with #WE = #CE = VIL and #OE = VIH will not accept commands on the rising
edge of #WE. The internal state machine is automatically reset to the read mode on power-up.
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相关代理商/技术参数 |
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| W49F002UT90B | 制造商:WINBOND 制造商全称:Winbond 功能描述:256K X 8 CMOS FLASH MEMORY |
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