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参数资料
| 型号： | W671520P |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | 模拟传输电路 |
| 英文描述： | TELECOM-SLIC, PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 13/42页 |
| 文件大小： | 1230K |
| 代理商： | W671520P |
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W671500 SERIES
C
PO
POL
I
1
75k
I
2
FIGURE 9: REVERSAL TIMING CONTROL
During Forward Active, the current from source I1 charges the external timing capacitor CPOL and the
switch is open. The internal resistor provides a clamping function for voltages on the POL node.
During Reverse Active, the switch closes and I2 (roughly twice I1) pulls current from I1 and the timing
capacitor. The current at the POL node provides the drive to a differential pair which controls the
reversal time (time) according to the following relationship.
CPOL
time
75000
----------------
=
(EQ. 32)
Polarized capacitors may be used for CPOL as the low voltage at the POL pin and minimal voltage
excursion of ±0.75V, are well suited to such capacitors.
7.2.3.2. Power Dissipation
The power dissipation equations for Forward Active operation described above also apply to Reverse
Active operation.
7.2.4. Ringing Mode
The Ringing mode (RNG, 100) provides linear amplification to support a variety of ringing waveforms.
A programmable Ring Trip function provides loop supervision and auto disconnect upon Ring Trip.
The device is designed to operate from the high battery during this mode.
7.2.4.1. Architecture
The device provides linear amplification to the signal applied to the Ringing Signal Input, VRS. The
differential ringing gain of the device is 80V/V. The circuit model for the ringing path is shown in the
following figure.
The voltage gain from the VRS input to the TIP output is 40V/V. The resistor ratio provides a gain of 8
and the current mirror provides a gain of 5. The voltage gain from the VRS input to the RING output is
-40V/V.
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