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参数资料
| 型号： | W681512W |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | 编解码器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PDSO20 |
| 封装： | PLASTIC, TSSOP-20 |
| 文件页数： | 3/36页 |
| 文件大小： | 448K |
| 代理商： | W681512W |
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W681512
Publication Release Date: September, 2005
- 11 -
Revision C13
PCMT will become low impedance when the Frame Sync signal FST is HIGH or when the 8 bit data
word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame
Sync signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted.
The internal decision logic will determine whether the next frame sync is a long or a short frame sync,
based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high
impedance for two frame sync cycles after every power down state. More detailed timing information
can be found in the interface timing section.
7.4.2. Short Frame Sync
The W681512 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is
HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge
of the bit-clock, the W681512 starts clocking out the data on the PCMT pin, which will also change
from high to low impedance state. The data transmit pin PCMT will go back to the high impedance
state halfway through the LSB. The Short Frame Sync operation of the W681512 is based on an 8-bit
data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after
the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine
whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse.
To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every
power down state. More detailed timing information can be found in the interface timing section.
7.4.3. General Circuit Interface (GCI)
The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface
consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects
channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data
clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK.
The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted
consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is
transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section.
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相关代理商/技术参数 |
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| W681512WG | 功能描述:IC VOICEBND CODEC 5V 1CH 20TSSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 编解码器 系列:- 标准包装:2,500 系列:- 类型:立体声音频 数据接口:串行 分辨率（位）:18 b ADC / DAC 数量:2 / 2 三角积分调变:是 S/N 比，标准 ADC / DAC (db):81.5 / 88 动态范围，标准 ADC / DAC (db):82 / 87.5 电压 - 电源，模拟:2.6 V ~ 3.3 V 电压 - 电源，数字:1.7 V ~ 3.3 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-WFQFN 裸露焊盘 供应商设备封装:48-TQFN-EP（7x7） 包装:带卷 (TR) |
| W681512WG TR | 功能描述:IC VOICEBND CODEC 5V 1CH 20TSSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 编解码器 系列:- 标准包装:2,500 系列:- 类型:立体声音频 数据接口:串行 分辨率（位）:18 b ADC / DAC 数量:2 / 2 三角积分调变:是 S/N 比，标准 ADC / DAC (db):81.5 / 88 动态范围，标准 ADC / DAC (db):82 / 87.5 电压 - 电源，模拟:2.6 V ~ 3.3 V 电压 - 电源，数字:1.7 V ~ 3.3 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-WFQFN 裸露焊盘 供应商设备封装:48-TQFN-EP（7x7） 包装:带卷 (TR) |
| W681512WG-TR | 制造商:Nuvoton Technology Corp 功能描述:IC VOICEBND CODEC 5V 1CH 20TSSOP |
| W681513 | 制造商:WINBOND 制造商全称:Winbond 功能描述:5V SINGLE-CHANNEL VOICEBAND CODEC FOR USB APPLICATIONS |
| W681513_05 | 制造商:WINBOND 制造商全称:Winbond 功能描述:5V SINGLE-CHANNEL VOICEBAND CODEC FOR USB APPLICATIONS |
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