参数资料
型号: W78E858A40DL
厂商: Nuvoton Technology Corporation of America
文件页数: 20/35页
文件大小: 0K
描述: IC MCU 8-BIT 32K FLASH 40-DIP
标准包装: 10
系列: W78
核心处理器: 8052
芯体尺寸: 8-位
速度: 40MHz
连通性: EBI/EMI,串行端口
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 40-DIP
包装: 管件
W78E858
6.3 A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a
±20 nS variation. The numbers below represent the performance expected
from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.
6.3.1
Clock Input Waveform
T
XTAL1
F
CH
CL
OP,
TCP
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Operating Speed
FOP
0
-
40
MHz
1
Clock Period
TCP
25
-
nS
2
Clock High
TCH
10
-
nS
3
Clock Low
TCL
10
-
nS
3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
6.3.2
Program Fetch Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Address Valid to ALE Low
TAAS
1 TCP-
Δ
-
nS
4
Address Hold from ALE Low
TAAH
1 TCP-
Δ
-
nS
1, 4
ALE Low to
PSEN Low
TAPL
1 TCP-
Δ
-
nS
4
PSEN Low to Data Valid
TPDA
-
2 TCP
nS
2
Data Hold after PSEN High
TPDH
0
-
1 TCP
nS
3
Data Float after PSEN High
TPDZ
0
-
1 TCP
nS
ALE Pulse Width
TALW
2 TCP-
Δ
2 TCP
-
nS
4
PSEN
Pulse Width
TPSW
3 TCP-
Δ
3 TCP
-
nS
4
Notes:
1. P0.0
P0.7, P2.0 P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "
Δ" (due to buffer driving delay and wire loading) is 20 nS.
Publication Release Date: April 22, 2008
- 27 -
Revision A8
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