参数资料
型号: W971GG6IB-25
厂商: WINBOND ELECTRONICS CORP
元件分类: DRAM
英文描述: 32M X 16 DDR DRAM, 0.4 ns, PBGA84
封装: 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84
文件页数: 5/86页
文件大小: 1360K
代理商: W971GG6IB-25
W971GG6IB
Publication Release Date: Oct. 23, 2009
- 13 -
Revision A02
7.2.2.3
Extend Mode Register Set Command (2), EMR (2)
( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "H", BA2 = "L" A0 to A12 =
Register data)
The extended mode register (2) controls refresh related features. The default value of the extended
mode register (2) is not defined, therefore the extended mode register (2) must be programmed during
initialization for proper operation.
The DDR2 SDRAM should be in all bank precharge state with CKE already high prior to writing into
the extended mode register (2). The mode register set command cycle time (tMRD) must be satisfied to
complete the write operation to the extended mode register (2). Mode register contents can be
changed using the same command and clock cycle requirements during normal operation as long as
all banks are in the precharge state.
BA1 BA0 A12
A11 A10
A9
A8A7
A6A5
A4A3
A2
A1A0
1
0
SELF
0*1
Address Field
Extended Mode Register (2)
0*1
BA2
0*1
BA1 BA0
MRS mode
0
1
11
MRS
EMR (1)
EMR (2)
EMR (3)
A7
1
0
Disable
High Temperature Self Refresh Rate Enable
Enable*2
Notes:
1. The rest bits in EMR (2) is reserved for future use and all bits in EMR (2) except A7, BA0, BA1 and BA2 must be programmed
to 0 when setting the extended mode register (2) during initialization.
2. When DRAM is operated at 85 °C ≤ TCASE ≤ 95 °C the extended Self Refresh rate must be enabled by setting bit A7 to "1"
before the Self Refresh mode can be entered.
Figure 4—EMR (2)
相关PDF资料
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W9751G6JB-25A 32M X 16 DDR DRAM, 0.4 ns, PBGA84
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