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参数资料
| 型号： | WB1356X |
| 英文描述： | Serial-Input Frequency Synthesizer |
| 中文描述： | 串行输入频率合成器 |
| 文件页数： | 9/10页 |
| 文件大小： | 201K |
| 代理商： | WB1356X |
WB1356
8
Notes:
6.
The MSB is loaded in first.
7.
Low count ratios may violate frequency limits of the phase detector.
Table 2. Shift Register Configuration[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Reference Counter and Configuration Bits
CNT1CNT2 R1
R2
R3
R4
R5
R6
R7
R8
R9
R10 R11 R12 R13 R14 R15
FC
IDO
TS
LD
FO
Programmable Counter bits
CNT1CNT2 A1A2
A3A4
A5
A6A7
B1B2
B3B4
B5B6B7B8
B9
B10 B11 PRE PD
Bit(s) Name
Function
CNT1, CNT2
Control Bits: Directs programming data to PLL1 (high frequency) or PLL2 (low frequency).
R1–R15
Reference Counter Setting Bits: 15 bits, R = 3 to 32767.[7]
FC
Phase Sense of the Phase Detector: Set to match the VCO polarity, H = + (Positive VCO transfer function).
IDO
Charge Pump Setting Bit: IDO HIGH = 4.4 mA, IDO LOW = 1.1 mA.
TS
Three-state Bit: Three-states the DO output for PLL2 and PLL1 when HIGH.
LD
Lock Detect: Directs the lock detect signal source pin 10. Pin 10 is HIGH with narrow low excursions when
locked. When not locked, this pin is LOW.
FO
Frequency Out: This bit can be set to read out reference or programmable divider at the LD pin for test purposes.
PRE
Prescaler: Prescaler divide bit, for PLL1 and PLL2 (LOW = 64/65, HIGH = 128/129).
PD
Power-down: LOW = power-up, HIGH = power-down. FIN is at a high-impedance state, respective B counter
is disabled, forces three-state at DO outputs and phase comparators are disabled. The reference counter is
disabled and the OSC input is high-impedance after both PLLs are powered down. Data can be input and latched
in the power-down state.
A1–A7
Swallow Counter Divide Ratio: A = 0 to 127.
B1–B11
Programmable Counter Divide Ratio: B = 3 to 2047.[7]
Table 3. FO/LD Pin Truth Table
FO (Bit 22)
LD (Bit 21)
FO/LD Pin Output State
PLL1
PLL2
PLL1
PLL2
0000
Disable
0001
PLL2 Lock Detect
0010
PLL1 Lock Detect
0011
PLL1/PLL2 Lock Detect
0
1
X
0
PLL2 Reference Divider Output
1
0
X
0
PLL1 Reference Divider Output
0
1
X
1
PLL2 Programmable Divider Output
1
0
X
1
PLL1 Programmable Divider Output
1101
PLL2 Counter Reset
1110
PLL1 Counter Reset
1111
PLL1/PLL2 Counter Reset
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