
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
126
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
4.5.3
Power-Down Mode
The LXT9785/LXT9785E incorporates numerous features to maintain the lowest power possible.
The device can be put into a low-power state via Register 0 as well as a near-zero power state with
the power down pin. When in power-down mode, the device is not capable of receiving or
transmitting packets.
The lowest power operation is achieved using the Global power-down pin, which is active High.
This pin powers down every circuit in the device, including all clocks. All registers are unaltered
and maintained when the Global PWRDWN pin is released.
Note:
The BGA15 package does not support the PWRDWN pin feature.
Individual ports (software power down) can be powered down using Register bit 0.11. This bit
powers down a significant portion of the port, but clocks to the register section remain active. This
allows the management interface to remain active during register power-down. The power-down
bit is active High.
Figure 13. Initialization Sequence
MDDIS Voltage
Level?
High
Low
MDIO Control
Mode
Hardware Control
Mode
Disable MDIO Writes
Reset MDIO Registers to
values read at H/W
Control Interface at last
Hardware Reset
Pass Control to MDIO
Interface
Power-up or Reset
Initialize MDIO Registers
Read H/W Control
Interface
Hardware
Reset?
Software
Reset?
Yes