- 您现在的位置：买卖IC网 > PDF目录297788 > WCMA2016U4X-FF70 (Electronic Theatre Controls, Inc.) 128K x 16 STATIC RAM PDF资料下载
参数资料
| 型号： | WCMA2016U4X-FF70 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 128K x 16 STATIC RAM |
| 中文描述： | 128K的× 16静态RAM |
| 文件页数： | 7/11页 |
| 文件大小： | 297K |
| 代理商： | WCMA2016U4X-FF70 |
WCMA2016U4X
5
Switching Characteristics Over the Operating Range[8]
Parameter
Description
70 ns
Min
Max
Unit
READ CYCLE
tRC
Read Cycle Time
70
ns
tAA
Address to Data Valid
70
ns
tOHA
Data Hold from Address Change
10
ns
tACE
CE LOW to Data Valid
70
ns
tDOE
OE LOW to Data Valid
35
ns
tLZOE
OE LOW to Low Z[9]
5
ns
tHZOE
OE HIGH to High Z[9, 11]
25
ns
tLZCE
CE LOW to Low Z[9]
10
ns
tHZCE
CE HIGH to High Z[9, 11]
25
ns
tPU
CE LOW to Power-Up
0
ns
tPD
CE HIGH to Power-Down
70
ns
tDBE
BHE / BLE LOW to Data Valid
70
ns
tLZBE
BHE / BLE LOW to Low Z[9]
5
ns
tHZBE
BHE / BLE HIGH to High Z[9, 11]
25
ns
WRITE CYCLE[12]
tWC
Write Cycle Time
70
ns
tSCE
CE LOW to Write End
60
ns
tAW
Address Set-Up to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
50
ns
tBW
BHE / BLE Pulse Width
60
ns
tSD
Data Set-Up to Write End
30
ns
tHD
Data Hold from Write End
0
ns
tHZWE
WE LOW to High Z[9, 11]
25
ns
tLZWE
WE HIGH to Low Z[9]
10
ns
Notes:
8.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and
output loading of the specified IOL/IOH and 30 pF load capacitance.
9.
At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less
than tLZWE for any given device.
10. If both byte enables are toggled together this value is 10ns
11.
tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the
edge of the signal that terminates the write..
相关PDF资料 |
PDF描述 |
|---|---|
| WDPI-3425J3525J-12 | 3425 MHz(Tx), 3525 MHz(Rx), DUPLEXER |
| WE-256K8-150CM | 256K X 8 EEPROM 5V, 150 ns, CDIP32 |
| WED3DG6418V10D1I | 16M X 64 SYNCHRONOUS DRAM MODULE, DMA144 |
| WED3DG6418V75D1I | 16M X 64 SYNCHRONOUS DRAM MODULE, DMA144 |
| WED3DG6418V10D1 | 16M X 64 SYNCHRONOUS DRAM MODULE, DMA144 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| WCMA4008C1X | 制造商:未知厂家 制造商全称:未知厂家 功能描述:512K x 8 Static RAM |
| WCMA4008C1X-GF70 | 制造商:Cypress Semiconductor 功能描述: |
| WCMA4016U1X | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256K x 16 Static RAM |
| WCMA4016U4X | 制造商:WEIDA 制造商全称:WEIDA 功能描述:256K x 16 Static RAM |
| WCMA4016U4X-FF70 | 制造商:Cypress Semiconductor 功能描述: |
发布紧急采购，3分钟左右您将得到回复。