参数资料
型号: WED3DL328V8BC
厂商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分类: DRAM
英文描述: 8M X 32 SYNCHRONOUS DRAM, 6 ns, PBGA119
封装: 14 X 22 MM, MO-163, BGA-119
文件页数: 26/27页
文件大小: 1195K
代理商: WED3DL328V8BC
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DL328V
June, 2002
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
Current State
CKE
Command
Action
Notes
Previous
Cycle
Current
Cycle
CE#
RAS#
CAS#
WE# BA0-1 A10-11
Self Refresh
H
X
INVALID
1
L
H
X
Exit Self Refresh with Device Deselect
2
L
H
L
H
X
Exit Self Refresh with No Operation
2
L
H
L
H
L
X
ILLEGAL
2
L
H
L
H
L
X
ILLEGAL
2
L
H
L
X
ILLEGAL
2
L
X
Maintain Self Refresh
Power Down
H
X
INVALID
1
L
H
X
Power Down Mode exit, all banks idle
2
L
H
L
X
ILLEGAL
2
H
X
L
H
L
X
Maintain Power Down Mode
2
All Banks Idle
H
X
Refer to the Idle State section of the
Current State Truth Table
3
H
L
H
X
H
L
H
X
H
L
H
X
CBR Refresh
H
L
OP Code
Mode Register Set
4
H
L
H
X
Refer to the Idle State section of the
Current State Truth Table
3
H
L
H
X
H
L
H
X
H
L
H
X
Entry Self Refresh
4
H
L
OP Code
Mode Register Set
L
X
Power Down
4
Any State other
than listed above
H
X
Refer to the Operations in the Current
State Truth Table
H
L
X
Begin Clock Suspend next cycle
5
L
H
X
Exit Clock Suspend next cycle
L
X
Maintain Clock Suspend
NOTES:
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS) must be satised before any
command other than Exit is issued.
3. The address inputs (A11-0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information.
4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
Must be a legal command as dened in the Current State Truth Table.
CLOCK ENABLE (CKE) TRUTH TABLE
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