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参数资料
| 型号： | WEDPN16M64V-100BI |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 16M X 64 SYNCHRONOUS DRAM MODULE, 7 ns, PBGA219 |
| 封装： | 25 X 25 MM, PLASTIC, BGA-219 |
| 文件页数： | 1/12页 |
| 文件大小： | 293K |
| 代理商： | WEDPN16M64V-100BI |
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPN16M64V-XBX
1
White Electronic Designs
The 128MByte (1Gb) SDRAM is a high-speed CMOS, dy-
namic random-access, memory using 4 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of the
chip’s 67,108,864-bit banks is organized as 8,192 rows by
512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmedsequence.
Accesses begin with the registration of an ACTIVE com-
mand, which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-12 select the row).
The address bits registered coincident with the READ or
WRITE command are used to select the starting column lo-
cation for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a
burst terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The 1Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compat-
ible with the 2
n rule of prefetch architectures, but it also
allows the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seam-
less, high-speed, random-access operation.
16Mx64 Synchronous DRAM
! High Frequency = 100, 125MHz
! Package:
219 Plastic Ball Grid Array (PBGA), 25 x 25mm
! Single 3.3V ±0.3V power supply
! Fully Synchronous; all signals registered on positive edge
of system clock cycle
! Internal pipelined operation; column address can be
changed every clock cycle
! Internal banks for hiding row access/precharge
! Programmable Burst length 1,2,4,8 or full page
! 8192 refresh cycles
! Commercial, Industrial and Military Temperature Ranges
! Organized as 16M x 64
User configurable as 2 x 16M x 32 and 4 x 16M x 16
! Weight: WEDPN16M64V-XBX - 2.5 grams typical
November 2003 Rev. 6
FEATURES
BENEFITS
! 41% SPACE SAVINGS
! Reduced part count
! Reduced trace lengths for lower parasitic capacitance
! Suitable for hi-reliability applications
! Laminate interposer for optimum TCE match
! Upgradeable to 32M x 64 density (contact factory for
information)
* This data sheet describes a product that is subject to change without notice.
GENERAL DESCRIPTION
相关PDF资料 |
PDF描述 |
|---|---|
| WEDPN16M64V-133B2C | 16M X 64 SYNCHRONOUS DRAM, 5.5 ns, PBGA219 |
| WEDPN16M64V-100B2C | 16M X 64 SYNCHRONOUS DRAM, 7 ns, PBGA219 |
| WEDPN16M64VR-100B2I | 16M X 64 SYNCHRONOUS DRAM MODULE, 6 ns, PBGA219 |
| WEDPN16M64VR-66BC | 16M X 64 SYNCHRONOUS DRAM MODULE, 7.5 ns, PBGA219 |
| WEDPN16M64VR-133BC | 16M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, PBGA219 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| WEDPN16M64V-100BM | 制造商:Microsemi Corporation 功能描述:16M X 64 SDRAM MODULE, 3.3V, 100 MHZ, 219 PBGA 25MM X 25MM, - Bulk |
| WEDPN16M64V-125B2C | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:16Mx64 Synchronous DRAM |
| WEDPN16M64V-125B2I | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:16Mx64 Synchronous DRAM |
| WEDPN16M64V-125B2M | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:16Mx64 Synchronous DRAM |
| WEDPN16M64V-125BC | 制造商:Microsemi Corporation 功能描述:16M X 64 SDRAM MODULE, 3.3V, 125 MHZ, 219 PBGA 25MM X 25MM, - Bulk |
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