参数资料
型号: WJLXT905LC.C2
厂商: INTEL CORP
元件分类: 网络接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP32
封装: ROHS COMPLIANT, MO-136BC, LQFP-32
文件页数: 40/40页
文件大小: 544K
代理商: WJLXT905LC.C2
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
Datasheet
9
Document Number: 249271
Revision Number: 004
Revision Date: 19-Oct-2005
10
14
CD
O
Carrier Detect. An output for notifying the controller that
activity exists on the network.
14
16
RCLK
O
Receive Clock. A recovered 10 MHz clock that is
synchronous to the received data and connects to the
controller receive clock input.
15
17
RXD
O
Receive Data. Output signal connected directly to the
receive data input of the controller.
16
18
LI
I
Link Enable. Controls link integrity test.
Enabled when LI is High.
Disabled when LI is Low.
17
19
RBIAS
I
Bias Circuitry. A 7.5 kW 1% resistor to ground at this pin
controls operating circuit bias.
18
20
DSQE
I
SQE Disable.
When DSQE is High, the SQE function is disabled.
When DSQE is Low, the SQE function is enabled.
Disable SQE for normal operation in Hub/Switch/Repeater
applications. Pulled Low internally1.
19
22
21
24
TPOP
TPON
O
Twisted-Pair Outputs. Differential outputs to the twisted-
pair cable. The outputs are pre-equalized.
23
24
25
26
MDO
MDI
I
Mode Select 0 and 1. Mode select pins determine controller
compatibility mode in accordance with Table 2. Pulled Low
internally1.
25
26
27
28
TPIP
TPIN
I
Twisted-Pair Inputs. A differential input pair from the twisted-
pair cable. Receive filter is integrated on-chip. Does not
require external filters.
Table 1.
Signal Descriptions (Sheet 2 of 2)
LQFP
Pin #
PLCC
Pin #
Symbol
I/O
Description
1. Externally pull-up or pull-down each pin separately using a 10 k
Ω, 1% termination resistor, or tie directly to
VCC or ground.
2. Do not allow this pin to float. If unused, tie High.
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