- 您现在的位置：买卖IC网 > PDF目录68583 > WJLXT971ALC.A4-857342 (CORTINA SYSTEMS INC) DATACOM, ETHERNET TRANSCEIVER, PQFP64 PDF资料下载
参数资料
| 型号： | WJLXT971ALC.A4-857342 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 17/80页 |
| 文件大小： | 931K |
| 代理商： | WJLXT971ALC.A4-857342 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
Page 24
Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver
LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
5.2 Network Media / Protocol
Support
Some registers are required and their functions are defined by the IEEE 802.3 standard.
The LXT972A PHY also supports additional registers for expanded functionality. The
LXT972A PHY supports multiple internal registers, each of which is 16 bits wide. Specific
register bits are referenced using an “X.Y” notation, where X is the register number (0-31)
and Y is the bit number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of
this interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read
and write operations are disabled and the Hardware Control Interface provides primary
configuration control. When MDDIS is Low, the MDIO port is enabled for both read and
write operations and the Hardware Control Interface is not used.
5.2.3.1.1
MDIO Addressing
The MDIO addressing protocol allows a controller to communicate with multiple PHYs.
Pin ADDR0 determines the PHY device address that is selected as follows.
Connect pin ADDR0 low to get PHY address 0.
Connect pin ADDR0 high to get PHY address 1.
5.2.3.1.2
MDIO Frame Structure
The physical interface consists of a data line (MDIO) and clock line (MDC). The frame
MDIO Interface timing is given in Section 7.0, Electrical Specifications.
5.2.3.1.3
MII Interrupts
Figure 5 shows the MII interrupt logic. The LXT972A PHY provides a hardware interrupt
pin (MDINT_L) and two dedicated interrupt registers, Register 18 and Register 19.
Register 18 provides interrupt enable and mask functions. Setting register bit 18.1 = 1
enables the device to request interrupt via the MDINT_L pin. An active Low on this pin
Figure 3
Management Interface Read Frame Structure
Figure 4
Management Interface Write Frame Structure
MDC
MDIO
(Read)
32 "1"s
011
0
Preamble
ST
Op Code
PHY Address
Turn
Around
Z0
A4
A3
A0
R4
R3
R0
Register Address
D15
D14
D1
Data
Write
Read
D15
D14
D1
D0
Idle
High Z
B3489-01
MDC
MDIO
(Write)
32 "1"s
0
101
Preamble
ST
Op Code
PHY Address
Turn
Around
1
0
A4
A3
A0
R4
R3
R0
Register Address
D15
D14
D1
D0
Data
Idle
Write
B3490-01
相关PDF资料 |
PDF描述 |
|---|---|
| WJLXT971ALC.A4-857344 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT971ALE.A4-857343 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT971ALE.A4-857346 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT972ALC.A4-857341 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT972ALC.A4-857345 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| WJLXT971ALE.A4 | 功能描述:IC XCVR 3V 2-SPEED ETHER 64LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| WJLXT971ALE.A4-857343 | 功能描述:TXRX ETH 10/100 SGL PORT 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:发射器 驱动器/接收器数:4/0 规程:RS422，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| WJLXT971ALE.A4-857346 | 制造商:Cortina Systems Inc 功能描述:PHY 1-CH 10Mbps/100Mbps 64-Pin LQFP T/R |
| WJLXT971CA4 | 制造商:Intel 功能描述: |
| WJLXT972ALC.A4 | 功能描述:IC TRANS 3.3V ETHERNET 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。