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| 型号： | WJLXT972ALC.A4SE001 |
| 厂商： | INTEL CORP |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | LEAD FREE, LQFP-64 |
| 文件页数： | 6/100页 |
| 文件大小： | 1046K |
| 代理商： | WJLXT972ALC.A4SE001 |
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Datasheet
13
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
2.0
Signal Descriptions
Intel recommends that all inputs and multi-function pins be tied to the inactive states and all
outputs be left floating, if unused.
Table 2.
LXT972A MII Signal Descriptions
LQFP
Pin#
Symbol
Type1
Signal Description
Data Interface Pins
60
59
58
57
TXD3
TXD2
TXD1
TXD0
I
Transmit Data. TXD is a bundle of parallel data signals that are driven by the
MAC. TXD<3:0> shall transition synchronously with respect to the TX_CLK.
TXD<0> is the least significant bit.
56
TX_EN
I
Transmit Enable. The MAC asserts this signal when it drives valid data on
TXD. This signal must be synchronized to TX_CLK.
55
TX_CLK
O
Transmit Clock. TX_CLK is sourced by the PHY in both 10 and 100 Mbps
operations. 2.5 MHz for 10 Mbps operation, 25 MHz for 100 Mbps operation.
45
46
47
48
RXD3
RXD2
RXD1
RXD0
O
Receive Data. RXD is a bundle of parallel signals that transition synchronously
with respect to the RX_CLK. RXD<0> is the least significant bit.
49
RX_DV
O
Receive Data Valid. The LXT972A asserts this signal when it drives valid data
on RXD. This output is synchronous to RX_CLK.
53
RX_ER
O
Receive Error. Signals a receive error condition has occurred. This output is
synchronous to RX_CLK.
54
TX_ER
I
Transmit Error. Signals a transmit error condition. This signal must be
synchronized to TX_CLK.
52
RX_CLK
O
Receive Clock. 25 MHz for 100 Mbps operation, 2.5 MHz for 10 Mbps
operation. Refer to “Clock Requirements” on page 21 in the Functional
Description section.
62
COL
O
Collision Detected. The LXT972A asserts this output when a collision is
detected. This output remains High for the duration of the collision. This signal
is asynchronous and is inactive during full-duplex operation.
63
CRS
O
Carrier Sense. During half-duplex operation (bit 0.8 = 0), the LXT972A asserts
this output when either transmitting or receiving data packets. During full-
duplex operation (bit 0.8 = 1), CRS is asserted during receive. CRS assertion is
asynchronous with respect to RX_CLK. CRS is de-asserted on loss of carrier,
synchronous to RX_CLK.
MII Control Interface Pins
3
MDDIS
I
Management Disable. When MDDIS is High, the MDIO is disabled from read
and write operations.
When MDDIS is Low at power up or reset, the Hardware Control Interface pins
control only the initial or “default” values of their respective register bits. After
the power-up/reset cycle is complete, bit control reverts to the MDIO serial
channel.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
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