参数资料
型号: WS128K32-25G2SMNA
元件分类: SRAM
英文描述: 128K X 32 MULTI DEVICE SRAM MODULE, 25 ns, CQFP68
封装: 0.300 INCH, HERMETIC SEALED, CERAMIC, QFP-68
文件页数: 3/6页
文件大小: 147K
代理商: WS128K32-25G2SMNA
White Microelectronics Phoenix, AZ (602) 437-1520
4
SRAM
MODULES
3
FIG. 2
AC TEST CIRCUIT
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75
.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
I
Current Source
D.U.T.
C
= 50 pf
eff
I
OL
V
1.5V
(Bipolar Supply)
Z
Current Source
OH
WS128K32-25G2SMX
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
AC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55
°C to +125°C)
Parameter
Symbol
-25
Units
Read Cycle
Min
Max
Read Cycle Time
tRC
25
ns
Address Access Time
tAA
25
ns
Output Hold from Address Change
tOH
0ns
Chip Select Access Time
tACS
25
ns
Output Enable to Output Valid
tOE
9ns
Chip Select to Output in Low Z
tCLZ1
5ns
Output Enable to Output in Low Z
tOLZ1
2ns
Chip Disable to Output in High Z
tCHZ1
10
ns
Output Disable to Output in High Z
tOHZ1
9ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55
°C to +125°C)
Parameter
Symbol
-25
Units
Write Cycle
Min
Max
Write Cycle Time
tWC
25
ns
Chip Select to End of Write
tCW
20
ns
Address Valid to End of Write
tAW
20
ns
Data Valid to End of Write
tDW
15
ns
Write Pulse Width
tWP
20
ns
Address Setup Time
tAS
0ns
Address Hold Time
tAH
0ns
Output Active from End of Write
tOW1
5ns
Write Enable to Output in High Z
tWHZ1
9ns
Data Hold Time
tDH
0ns
1. This parameter is guaranteed by design but not tested.
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