- 您现在的位置：买卖IC网 > PDF目录140379 > WV3DG72256V7AD2MG (WHITE ELECTRONIC DESIGNS CORP) 256M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 PDF资料下载
参数资料
| 型号： | WV3DG72256V7AD2MG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| 封装： | ROHS COMPLIANT, DIMM-168 |
| 文件页数： | 5/9页 |
| 文件大小： | 253K |
| 代理商： | WV3DG72256V7AD2MG |
WV3DG72256V-AD2
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2006
Rev. 0
AC OPERATING TEST CONDITIONS
VCC = 3.3V, 0°C
≤ TA ≤ 70°C
Parameter
Value
Units
AC Input level (VIN/VIL)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
AC OPERATING TEST CONDITIONS
Parameter
Symbol
Value
Units
Notes
133/100
Row active to row active delay
tRRD(MIN)
15
ns
1
RAS# to CAS# delay
tRCD(MIN)
20
ns
1
Row Precharge time
tRP(MIN)
20
ns
1
Row active time
tRAS(MIN)
45
ns
1
tRAS(MAX)
100
s
Row cycle time
tRC(MIN)
65
ns
1
Last data in to row precharge
tRDL(MIN)
2
CLK
2
Last data in to Active delay
tDAL(MIN)
2 CLK + tRP
—
Last data in to new col. address delay
tCDL(MIN)
1
CLK
1
Last data in to burst stop
tBDL(MIN)
1
CLK
2
Col. address to col. address delay
tCCD(MIN)
1
CLK
2
Number of valid output data
CAS Latency = 3
2
CLK
3
Cas Latency = 2
1
ea
4
Notes: 1. The minimum number of clock cycles is determined by driving the minimum time required with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
3.3V
1220
870
Output
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=2.4V, IOL=-2mA
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
50pF
VTT=1.4V
50
Output
50pF
Z0 = 50
PRELIMINARY*
相关PDF资料 |
PDF描述 |
|---|---|
| WS128K32-120G4C | 512K X 8 MULTI DEVICE SRAM MODULE, 120 ns, CQFP68 |
| WS128K32-35HSME | 512K X 8 MULTI DEVICE SRAM MODULE, 35 ns, CHIP66 |
| WS128K32N-45G4CE | 512K X 8 MULTI DEVICE SRAM MODULE, 45 ns, CQFP68 |
| WE32K32N-150G2Q | 128K X 8 EEPROM 5V MODULE, 150 ns, QMA68 |
| WS128K32N-25HC | 512K X 8 MULTI DEVICE SRAM MODULE, 25 ns, HIP66 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| WV3DG72256V-AD2 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 SDRAM, REGISTERED |
| WV3DG7266V10D1 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB -2x32Mx72 SDRAM, UNBUFFERED, w/PLL |
| WV3DG7266V75D1 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB -2x32Mx72 SDRAM, UNBUFFERED, w/PLL |
| WV3DG7266V7D1 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB -2x32Mx72 SDRAM, UNBUFFERED, w/PLL |
| WV3DG7266V-D1 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB -2x32Mx72 SDRAM, UNBUFFERED, w/PLL |
发布紧急采购，3分钟左右您将得到回复。