- 您现在的位置：买卖IC网 > PDF目录103809 > WV3EG265M72EFSU265D4ING (WHITE ELECTRONIC DESIGNS CORP) 128M X 72 DDR DRAM MODULE, 0.75 ns, ZMA200 PDF资料下载
参数资料
| 型号： | WV3EG265M72EFSU265D4ING |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.75 ns, ZMA200 |
| 封装： | ROHS COMPLIANT, SODIMM-200 |
| 文件页数： | 8/11页 |
| 文件大小： | 171K |
| 代理商： | WV3EG265M72EFSU265D4ING |
WV3EG265M72EFSU-D4
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2006
Rev. 0
ADVANCED
ICC SPECIFICATIONS AND CONDITIONS
VCC, VCCQ = +2.5V ±0.2V
SYM
PARAMETER/CONDITION
MAX
UNITS
DDR333
@CL=2.5
DDR266
@CL=2
DDR266
@CL=2.5
ICC0*
OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN);
DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing
once every two clock cycles
1,270
1,180
mA
ICC1*
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN);
tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
1,540
1,450
mA
ICC2P**
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down
mode; tCK = tCK (MIN); CKE = (LOW)
370
mA
ICC2F**
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE =
HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ,
DQS, and DM
820
mA
ICC3P**
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode;
tCK = tCK (MIN); CKE = LOW
820
mA
ICC3N**
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS
(MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
1,090
mA
ICC4R*
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA
1,585
1,450
mA
ICC4W*
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle
1,675
1,495
mA
ICC5**
AUTO REFRESH BURST CURRENT:
tREFC = tRFC (MIN)
3,970
3,790
mA
ICC6**
SELF REFRESH CURRENT: CKE ≤ 0.2V
370
mA
ICC7*
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto
precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only
during Active READ, or WRITE commands
3,565
3,250
mA
Note: ICC specication is based on SAMSUNG components. Other DRAM Manufacturers specication may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reects all module ranks in this operating condition.
相关PDF资料 |
PDF描述 |
|---|---|
| W3EG72129S335JD3S | 128M X 72 DDR DRAM MODULE, 0.7 ns, DMA184 |
| W3HG264M72EEU806D6SG | 128M X 72 DDR DRAM MODULE, DMA240 |
| WE512K8250CC | 512K X 8 EEPROM 5V MODULE, 250 ns, CDIP32 |
| WE512K8-150CQA | 512K X 8 EEPROM 5V MODULE, 150 ns, CDIP32 |
| WF4M32-120G4TC5 | 4M X 32 FLASH 5V PROM MODULE, 120 ns, CQFP68 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| WV3EG265M72EFSU265D4IS | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU265D4ISG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU265D4M | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU265D4MG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU265D4N | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
发布紧急采购，3分钟左右您将得到回复。