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参数资料
| 型号： | WV3EG64M72ETSU335D3SG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, DMA184 |
| 封装： | ROHS COMPLIANT, DIMM-184 |
| 文件页数： | 5/10页 |
| 文件大小： | 213K |
| 代理商： | WV3EG64M72ETSU335D3SG |
White Electronic Designs
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
October 2005
Rev. 0
PRELIMINARY
WV3EG64M72ETSU-D3
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 to 3.6
V
Voltage on VCC supply relative to VSS
VCC
-1.0 to 3.6
V
Voltage on VCCQ supply relative to VSS
VCCQ
-1.0 to 3.6
V
Storage Temperature
TSTG
-55 to +150
°C
Operating Temperature
TA
0 to +70
°C
Power Dissipation
PD
9W
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C TA 70°C, VCC = VCCQ = 2.5V ± 0.2V
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage DDR266/DDR333 (nominal VCC of 2.5V)
VCC
2.3
2.7
I/O Supply voltage DDR266/DDR333 (nominal VCC of 2.5V)
VCCQ
2.3
2.7
V
I/O Reference voltage
VREF
0.49*VCCQ
0.51*VCCQ
V1
I/O Termination voltage
VTT
VREF-0.04
VREF+0.04
V
2
Input logic high voltage
VIH(DC)
VREF+0.15
VCCQ+0.30
V
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
Input voltage level, CK and CK#
VIN(DC)
-0.3
VCCQ+0.30
V
Input differential voltage, CK and CK#
VID(DC)
0.36
VCCQ+0.60
V
3
Input crossing point voltage, CK and CK#
VIX(DC)
0.3
VCCQ+0.60
V
Input leakage current
Addr, CAS#,
RAS#, WE#
II
-18
18
uA
CS#, CKE
-18
18
uA
CK, CK#
-6
6
uA
DM
-2
2
uA
Output leakage current
IOZ
-5
5
uA
Output high current (normal strengh); VOUT = V +0.84V
IOH
-16.8
—
mA
Output high current (normal strengh); VOUT = VTT -0.84V
IOL
16.8
—
mA
Output high current (half strengh); VOUT = VTT +0.45V
IOH
-9
—
mA
Output high current (half strengh); VOUT = VTT -0.45V
IOL
9—
mA
NOTES:
1. VREF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed ±2% of the DC
value
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = VCCQ = 2.5V
Parameter
Symbol
Min
Max
Unit
Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#)
CIN1
22
31
pF
Input Capacitance (CKE0)
CIN2
22
31
pF
Input Capacitance (CS0#)
CIN3
22
31
pF
Input Capacitance (CK0 to CK2, CK0# to CK2#)
CIN4
10
13
pF
Input Capacitance (DM0-DM7)
CIN5
89
pF
Data and DQS input/output capacitance (DQ0-DQ63)
COUT1
89
pF
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相关代理商/技术参数 |
参数描述 |
|---|---|
| WV3EG64M72ETSU-D3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR SDRAM UNBUFFERED |
| WV3EG72M64ETSU335D3MG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR SDRAM UNBUFFERED |
| WV3EG72M64ETSU335D3SG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR SDRAM UNBUFFERED |
| WV3H2256M72AER403D6IMG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:4GB - 2x256Mx72 DDR2 SDRAM RDIMM, w/PLL |
| WV3H2256M72AER403D6ISG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:4GB - 2x256Mx72 DDR2 SDRAM RDIMM, w/PLL |
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