参数资料
型号: WV3HG64M72AER403AD6SG
厂商: WHITE ELECTRONIC DESIGNS CORP
元件分类: DRAM
英文描述: 64M X 72 DDR DRAM MODULE, 0.6 ns, DMA240
封装: ROHS COMPLIANT, DIMM-240
文件页数: 6/10页
文件大小: 180K
代理商: WV3HG64M72AER403AD6SG
WV3HG64M72AER-AD6
October 2006
Rev. 2
ADVANCED
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Symbol
Proposed Conditions
534
403
Units
ICC0
Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
2,420
2,250
mA
ICC1
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC);
CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as IDAD6W
2,640
2,400
mA
ICC2P
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
730
670
mA
ICC2Q
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
1,110
1,040
mA
ICC2N
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
1,090
1,060
mA
ICC3P
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0mA
1,190
1,130
mA
Slow PDN Exit MRS(12) = 1mA
600
570
mA
ICC3N
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,840
1,730
mA
IDAD6W
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP
= tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
3,550
2,810
mA
IDAD6R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDAD6W
3,230
2,730
mA
ICC5B
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
3,610
3,430
mA
ICC6
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
740
680
mA
ICC7
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC =
tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for
detailed timing conditions
5,540
5,210
mA
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WV3HG64M72EER403D6IMG 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR2 SDRAM REGISTERED DIMM, w/PLL
WV3HG64M72EER403D6ISG 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR2 SDRAM REGISTERED DIMM, w/PLL