参数资料
| 型号： | X1228V14-2.7 |
| 厂商： | Intersil |
| 文件页数： | 5/29页 |
| 文件大小： | 0K |
| 描述： | IC RTC/CAL/CPU SUP EE 14-TSSOP |
| 标准包装： | 95 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，监控器，监视计时器 |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.8 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 管件 |
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13
FN8100.4
May 18, 2006
STATUS REGISTER (SR)
The Status Register is located in the CCR memory
map area at address 003Fh. This is a volatile register
only and is used to control the WEL and RWEL write
enable latches, read two power status and two alarm
bits. This register is separate from both the array and
the Clock/Control Registers (CCR).
Table 2. Status Register (SR)
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from VBACK, not VCC. It is a read-only bit and is set/reset
by hardware (X1228 internally). Once the device begins
operating from VCC, the device sets this bit to “0”.
AL1, AL0: Alarm bits—Volatile
These bits announce if either alarm 0 or alarm 1 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read opera-
tion is complete.
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both the
RWEL and WEL bits to be set in a specific sequence.
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and mem-
ory array during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to the CCR or any array
address will be ignored (no acknowledge will be issued
after the Data Byte). The WEL bit is set by writing a “1”
to the WEL bit and zeroes to the other bits of the Status
Register. Once set, WEL remains set until either reset
to 0 (by writing a “0” to the WEL bit and zeroes to the
other bits of the Status Register) or until the part powers
up again. Writes to WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next operation
immediately after the stop condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a “1” after a total power failure. This is
a read only bit that is set by hardware (X1228 inter-
nally) when the device powers up after having lost all
power to the device (both VCC and VBACK go to 0V).
The bit is set regardless of whether VCC or VBACK is
applied first. The loss of only one of the supplies does
not set the RTCF bit to “1”. On power-up after a total
power failure, all registers are set to their default
states and the clock will not increment until at least
one byte is written to the clock register. The first valid
write to the RTC section after a complete power failure
resets the RTCF bit to “0” (writing one byte is suffi-
cient).
Unused Bits:
This device does not use bits 3 or 4 in the SR, but must
have a zero in these bit positions. The Data Byte output
during a SR read will contain zeros in these bit locations.
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
Block Protect Bits—BP2, BP1, BP0
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3 .
Table 3. Block Protect Bits
Watchdog Timer Control Bits—WD1, WD0
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
Addr
7
6
5
4
3
2
1
0
003Fh
BAT
AL1
AL0
0
RWEL
WEL
RTCF
Default
0
1
BP
2
BP
1
BP
0 Protected Addresses
X1228
Array Lock
0
None
None (Default)
0
1
180h - 1FFh
Upper 1/4
0
1
0
100h - 1FFh
Upper 1/2
0
1
000h - 1FFh
Full Array
1
0
000h - 03Fh
First Page
1
0
1
000h - 07Fh
First 2 pgs
1
0
000h - 0FFh
First 4 pgs
1
000h - 1FFh
First 8 pgs
X1228
相关PDF资料 |
PDF描述 |
|---|---|
| X1228V14 | IC RTC/CAL/CPU SUP EE 14-TSSOP |
| X1228S14Z-4.5A | IC RTC/CAL/CPU SUP EE 14-SOIC |
| X1228S14Z-2.7A | IC RTC/CAL/CPU SUP EE 14-SOIC |
| X1228S14Z-2.7 | IC RTC/CAL/CPU SUP EE 14-SOIC |
| X1228S14Z | IC RTC/CAL/CPU SUP EE 14-SOIC |
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