参数资料
| 型号： | X1288S16T1 |
| 厂商： | Intersil |
| 文件页数： | 15/27页 |
| 文件大小： | 0K |
| 描述： | IC RTC/CAL/CPU SUP EE 16-SOIC |
| 标准包装： | 1,000 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，监控器，监视计时器 |
| 时间格式： | HH:MM:SS:hh（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.8 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
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22
FN8102.3
April 14, 2006
APPLICATION SECTION
CRYSTAL OSCILLATOR AND TEMPERATURE
COMPENSATION
Intersil has now integrated the oscillator compensation
circuity on-chip, to eliminate the need for external compo-
nents and adjust for crystal drift over temperature and
enable very high accuracy time keeping (<5ppm drift).
The Intersil RTC family uses an oscillator circuit with on-
chip crystal compensation network, including adjustable
load-capacitance. The only external component required
is the crystal. The compensation network is optimized for
operation with certain crystal parameters which are com-
mon in many of the surface mount or tuning-fork crystals
available today. Table 7 summarizes these parameters.
Table 8 contains some crystal manufacturers and part
numbers that meet the requirements for the Intersil RTC
products.
The turnover temperature in Table 7 describes the tem-
perature where the apex of the of the drift vs. tempera-
ture curve occurs. This curve is parabolic with the drift
increasing as (T-T0)2. For an Epson MC-405 device, for
example, the turnover temperature is typically 25°C, and
a peak drift of >110ppm occurs at the temperature
extremes of -40 and +85°C. It is possible to address this
variable drift by adjusting the load capacitance of the
crystal, which will result in predictable change to the crys-
tal frequency. The Intersil RTC family allows this adjust-
ment over temperature since the devices include on-chip
load capacitor trimming. This control is handled by the
Analog Trimming Register, or ATR, which has 6 bits of
control . The load capacitance range covered by the ATR
circuit is approximately 3.25pF to 18.75pF, in 0.25pf
increments. Note that actual capacitance would also
include about 2pF of package related capacitance. In-cir-
cuit tests with commercially available crystals demon-
strate that this range of capacitance allows frequency
control from +116ppm to -37ppm, using a 12.5pF load
crystal.
In addition to the analog compensation afforded by the
adjustable load capacitance, a digital compensation fea-
ture is available for the Intersil RTC family. There are
three bits known as the Digital Trimming Register or
DTR, and they operate by adding or skipping pulses in
the clock signal. The range provided is ±30ppm in incre-
ments of 10ppm. The default setting is 0ppm. The DTR
control can be used for coarse adjustments of fre-
quency drift over temperature or for crystal initial accu-
racy correction.
0
Slave
Address
Word
Address 1
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
1
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
A
C
K
Word
Address 0
1
10
1
11
FIGURE 17. RANDOM ADDRESS READ SEQUENCE
Data
(2)
S
t
o
p
Slave
Address
Data
(n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data
(n-1)
A
C
K
A
C
K
(n is any integer greater than 1)
Data
(1)
FIGURE 18. SEQUENTIAL READ SEQUENCE
X1288
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