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参数资料
| 型号： | X24C45SM |
| 厂商： | INTERSIL CORP |
| 元件分类： | DRAM |
| 英文描述： | Serial AUTOSTORE NOVRAM |
| 中文描述： | 16 X 16 NON-VOLATILE SRAM, 375 ns, PDSO8 |
| 封装： | PLASTIC, SOIC-8 |
| 文件页数： | 4/14页 |
| 文件大小： | 58K |
| 代理商： | X24C45SM |
4
X24C45
WRITE
The WRITE instruction contains the 4-bit address of the
word to be written. The write instruction is immediately
followed by the 16-bit word to be written. CE must
remain HIGH during the entire operation. CE must go
LOW before the next rising edge of SK. If CE is brought
LOW prematurely (after the instruction but before 16 bits
of data are transferred), the instruction register will be
reset and the data that was shifted-in will be written to
RAM.
If CE is kept HIGH for more than 24 SK clock cycles (8-bit
instruction plus 16-bit data), the data already shifted-in will
be overwritten.
READ
The READ instruction contains the 4-bit address of the
word to be accessed. Unlike the other six instructions, I
0
of the instruction word is a “don’t care”. This provides two
advantages. In a design that ties both DI and DO
together, the absence of an eighth bit in the instruction
allows the host time to convert an I/O line from an output
to an input. Secondly, it allows for valid data output
during the ninth SK clock cycle.
D0, the first bit output during a read operation, is trun-
cated. That is, it is internally clocked by the falling edge
of the eighth SK clock; whereas, all succeeding bits are
clocked by the rising edge of SK (refer to Read Cycle
Diagram).
LOW POWER MODE
When CE is LOW, non-critical internal devices are
powered-down, placing the device in the standby power
mode, thereby minimizing power consumption.
AUTOSTORE Feature
The AUTOSTORE instruction (ENAS) sets the
“AUTOSTORE enable” latch, allowing the X24C45 to
automatically perform a store operation when V
CC
falls
below the AUTOSTORE threshold (V
ASTH
).
WRITE PROTECTION
The X24C45 provides two software write protection
mechanisms to prevent inadvertent stores of unknown
data.
Power-Up Condition
Upon power-up the “write enable” and “AUTOSTORE
enable” latches are in the reset state, disabling any store
operation.
Unknown Data Store
The “previous recall” latch must be set after power-up.
It may be set only by performing a software or hardware
recall operation, which assures that data in all RAM
locations is valid.
SYSTEM CONSIDERATIONS
Power-Up Recall
The X24C45 performs a power-up recall that transfers
the E
2
PROM contents to the RAM array. Although the
data may be read from the RAM array, this recall does
not set the “previous recall” latch. During this power-up
recall operation, all commands are ignored. Therefore,
the host should delay any operations with the X24C45 a
minimum of t
PUR
after V
CC
is stable.
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