参数资料
型号: X4003S8IZ
厂商: Intersil
文件页数: 8/16页
文件大小: 0K
描述: IC SUPERVISOR CPU I2C 8-SOIC
标准包装: 100
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 100 ms
电压 - 阀值: 4.38V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
X4003, X4005
SCL
SDA
START
STOP
FIGURE 7. VALID START AND STOP CONDITIONS
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
1
8
9
ACKNOWLEDGE
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
ADDRESS
1 0 1 1 0 0 1 0
A
C
K
BYTE
ADDRESS
1 1 1 1 1 1 1 1
A
C
K
DATA
A
C
K
SLAVE
FIGURE 9. WRITE CONTROL REGISTER SEQUENCE
Serial Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. See Figure 7.
Serial Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus. See Figure 7.
Serial Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
8
SDA line LOW to acknowledge that it received the eight bits
of data. Refer to Figure 8.
The device will respond with an acknowledge after
recognition of a start condition and the correct contents of
the slave address byte. Acknowledge bits are also provided
by the X4003/4005 after correct reception of the control
register address byte, after receiving the byte written to the
control register and after the second slave address in a read
question (see Figures 9 and 10).
Serial Write Operations
Slave Address Byte
Following a start condition, the master must output a slave
address byte. This byte consists of several parts:
? a device type identifier that is always ‘1011’.
? two bits of ‘0’.
? one bit of the slave command byte is a R/W bit. The R/W
bit of the slave address byte defines the operation to be
FN8113.2
June 30, 2008
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