参数资料
| 型号： | X40235S16I-AT1 |
| 厂商： | Intersil |
| 文件页数： | 18/36页 |
| 文件大小： | 0K |
| 描述： | IC VOLTAGE MON TRPL EE 16-SOIC |
| 标准包装： | 1,000 |
| 类型： | 多压监控器 |
| 监视电压数目： | 3 |
| 输出： | 开路漏极，开路漏极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 1.75V，2.2V，2.95V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页当前第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
X40231, X40233, X40235, X40237, X40239
CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CR) Register Write Enable
PUP1
V2FS
V3FS
BL1
BL0
RWEL
WEL
PUP0
status of the X4023x. Therefore, in order to write to
any of the bits of the CR Register (except WEL), the
NV
NV
NV
NV
RWEL bit must first be set to “1”. The RWEL bit is a
Bit(s)
WEL
RWEL
V2FS
V3FS
BL1 - BL0
PUP1 - PUP0
Description
Write Enable Latch bit
Register Write Enable Latch bit
V2MON Output Flag Status
V3MON Output Flag Status
Sets the Block Lock partition
Sets the Power-on Reset time
volatile bit that powers up in the disabled, LOW (“0”)
state.
It must be noted that the RWEL bit can only be set,
once the WEL bit has first been enabled (See "CR
Register Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of three cases:
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
Figure 17. CR Register Format
CONTROL AND STATUS REGISTER
The Control and Status (CR) Register provides the user
with a mechanism for changing and reading the status
of various parameters of the X4023x (See Figure 17).
The CR register is a combination of both volatile and
nonvolatile bits. The nonvolatile bits of the CR register
retain their stored values even when V CC is powered
down, then powered back up. The volatile bits how-
ever, will always power-up to a known logic state “0”
(irrespective of their value at power-down).
A detailed description of the function of each of the CR
register bits follows:
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the
entire X4023x device. This bit must first be enabled
—After a successful write operation to any bits of the CR
register has been completed (See Figure 18).
—When the X4023x is powered down.
—When attempting to write to a Block Lock protected
region of the EEPROM memory (See "BL1, BL0: Block
Lock protection bits - (Nonvolatile)", below).
BL1, BL0: Block Lock protection bits - (Nonvolatile)
The Block Lock protection bits (BL1 and BL0) are used
to:
—Inhibit a write operation from being performed to cer-
tain addresses of the EEPROM memory array
—Inhibit a DCP write operation (changing the “wiper
position”).
The region of EEPROM memory which is protected /
locked is determined by the combination of the BL1
and BL0 bits written to the CR register. It is possible to
lock the regions of EEPROM memory shown in the
table below:
before ANY write operation (to DCPs, EEPROM mem-
Protected Addresses
Partition of array
ory array, or the CR register). If the WEL bit is not first
BL1 BL0
(Size)
locked
enabled, then ANY proceeding (volatile or nonvolatile)
write operation to DCPs, EEPROM array, as well as
the CR register, is aborted and no ACKNOWLEDGE is
issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the
0
0
1
1
0
1
0
1
None (Default)
C0 h - FF h (64 bytes )
80 h - FF h (128 bytes )
00 h - FF h (256 bytes)
None (Default)
Upper 1/4
Upper 1/2
All
disabled, LOW (0) state. The WEL bit is enabled / set
by writing 00000010 to the CR register. Once enabled,
the WEL bit remains set to “1” until either it is reset to
“0” (by writing 00000000 to the CR register) or until the
X4023x powers down, and then up again.
Writes to the WEL bit do not cause an internal high
voltage write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition
is executed in the CR Write command sequence (See
Figure 18).
18
If the user attempts to perform a write operation on a
protected region of EEPROM memory, the operation
is aborted without changing any data in the array.
FN8115.0
April 11, 2005
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| X40235S16I-B | 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:100 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:- 复位:低有效 复位超时:最小为 100 ms 电压 - 阀值:4.38V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:8-TSSOP 包装:管件 |
| X40235S16I-BT1 | 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:100 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:- 复位:低有效 复位超时:最小为 100 ms 电压 - 阀值:4.38V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:8-TSSOP 包装:管件 |
| X40237 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP |
| X40237S16I-A | 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:100 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:- 复位:低有效 复位超时:最小为 100 ms 电压 - 阀值:4.38V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:8-TSSOP 包装:管件 |
| X40237S16I-AT1 | 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:100 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:- 复位:低有效 复位超时:最小为 100 ms 电压 - 阀值:4.38V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:8-TSSOP 包装:管件 |
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