参数资料
型号: X40420V14I-CT1
厂商: Intersil
文件页数: 15/25页
文件大小: 0K
描述: IC VOLT MON DUAL SUP/SW 14-TSSOP
标准包装: 2,500
类型: 多压监控器
监视电压数目: 2
输出: 开路漏极,开路漏极
复位: 高有效/低有效
复位超时: 可调节/可选择
电压 - 阀值: 1.6V,2.9V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-TSSOP
包装: 带卷 (TR)
X40420, X40421
Figure 15. Random Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
t
Slave
Address
1 01
0 0
0
A
C
K
Byte
Address
A
C
K
S
t
a
r
t
Slave
Address
1
A
C
K
Data
S
t
o
p
Figure 16. X40410/11 Addressing
Slave Byte
General Purpose Memory
1
0
1
0
0
0
A8 R/W
Control Register
Fault Detection Register
1
1
0
0
1
1
1
1
0
0
0
0
1
0
R/W
R/W
Word Address
General Purpose Memory A7
A6 A5 A4 A3 A2 A1
A0
Control Register
Fault Detection Register
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Word Address
The word address is either supplied by the master or
obtained from an internal counter.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for t PURST .
Figure 17. Sequential Read Sequence
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
Signals from
the Master
Slave
Address
A
C
K
A
C
K
A
C
K
S
t
o
p
SDA Bus
1
Signals from
the Slave
A
C
K
Data
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
15
May 25, 2006
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