参数资料
| 型号： | X40430V14I-AT1 |
| 厂商： | Intersil |
| 文件页数： | 11/26页 |
| 文件大小： | 0K |
| 描述： | IC VOLT MON TRPL EEPROM 14-TSSOP |
| 标准包装： | 2,500 |
| 类型： | 多压监控器 |
| 监视电压数目： | 3 |
| 输出： | 开路漏极，推挽式 |
| 复位： | 高有效/低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 1.7V，2.9V，4.6V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
X40430, X40431, X40434, X40435
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeroes to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.
BP: Block Protect Bits (Nonvolatile)
The Block Protect Bit BP, determines which blocks of
the array are write protected. A write to a protected
block of memory is ignored. The block protect bit will
prevent write operations to half or none of the array.
– Write one byte value to the Control Register that has
all the control bits set to the desired state. The Control
register can be represented as qxys 001 r in binary,
where xy are the WD bits, s is the BP bit and qr are the
power-up bits. This operation proceeded by a start and
ended with a stop bit. Since this is a nonvolatile write
cycle it will take up to 10ms (max.) to complete. The
RWEL bit is reset by this cycle and the sequence must
be repeated to change the nonvolatile bits again. If bit
2 is set to ‘1’ in this third step ( qxys 011 r ) then the
RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and
BP bits remain unchanged. Writing a second byte to
BP
0
1
Protected Addresses
(Size)
None
100h – 1FFh (256 bytes)
Memory Array
Lock
None
Upper Half of
Memory Array
the control register is not allowed. Doing so aborts the
write operation and returns a NACK.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
PUP1, PUP0: Power-up Bits (Nonvolatile)
The Power-up bits, PUP1 and PUP0, determine the
t PURST time delay. The nominal power-up times are
shown in the following table.
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
PUP1
0
0
1
1
PUP0
0
1
0
1
Power-on Reset Delay ( t PURST )
50ms
200ms (factory setting)
400ms
800ms
tile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
Notes: 1. t PURST is set to 200ms as factory default.
2. Watch Dog Timer bits are shipped disabled.
FAULT DETECTION REGISTER
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
The Fault Detection Register (FDR) provides the user
the status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and Three
WD1
WD0
Watchdog Time Out Period
Low Voltage Fail bits are volatile
0
0
1.4 seconds
7
6
5
4
3
2
1
0
0
1
200 milliseconds
LV1F
LV2F LV3F WDF
MRF
0
0
0
1
1
0
1
25 milliseconds
disabled (factory setting)
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceded by a start and ended with a stop).
– Write a 06H to the Control Register to set the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
11
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
There is no need to set the WEL or RWEL in the
control register to access this FDR.
FN8251.1
May 24, 2006
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相关代理商/技术参数 |
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|---|---|
| X40430V14I-B | 功能描述:IC VOLT MON TRPL EEPROM 14-TSSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:100 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:- 复位:低有效 复位超时:最小为 100 ms 电压 - 阀值:4.38V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:8-TSSOP 包装:管件 |
| X40430V14I-BT1 | 功能描述:IC VOLT MON TRPL EEPROM 14-TSSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:100 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:- 复位:低有效 复位超时:最小为 100 ms 电压 - 阀值:4.38V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:8-TSSOP 包装:管件 |
| X40430V14I-C | 功能描述:IC VOLT MON TRPL EEPROM 14-TSSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:100 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:- 复位:低有效 复位超时:最小为 100 ms 电压 - 阀值:4.38V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:8-TSSOP 包装:管件 |
| X40430V14I-CT1 | 功能描述:IC VOLT MON TRPL EEPROM 14-TSSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:100 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:- 复位:低有效 复位超时:最小为 100 ms 电压 - 阀值:4.38V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:8-TSSOP 包装:管件 |
| X40430V14IZ-AT1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
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