参数资料
型号: X4163PI-2.7
厂商: Intersil
文件页数: 4/22页
文件大小: 0K
描述: IC SUPERVISOR CPU 16K EE 8-DIP
标准包装: 150
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 100 ms
电压 - 阀值: 2.62V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-DIP
包装: 管件
X4163, X4165
PIN CONFIGURATION
8 Ld JEDEC SOIC
8 Ld TSSOP
S 0
S 1
RESET/RESET
V SS
1
2
3
4
8
7
6
5
V CC
WP
SCL
SDA
WP
V CC
S 0
S 1
1
2
3
4
8
7
6
5
SCL
SDA
V SS
RESET/RESET
PIN FUNCTION
Pin
(SOIC)
1
2
3
4
5
Pin
(TSSOP)
3
4
5
6
7
Name
S 0
S 1
RESET/
RESET
V SS
SDA
Function
Device Select Input
Device Select Input
Reset Output . RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V CC falls below the minimum V CC sense level. It will remain
active until V CC rises above the minimum V CC sense level for 250ms.
RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains
either HIGH or LOW longer than the selectable Watchdog time out period. A falling
edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET
goes active on power up and remains active for 250ms after the power supply sta-
bilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
6
7
8
8
1
2
SCL
WP
V CC
4
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
Supply Voltage
FN8120.2
November 26, 2007
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