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参数资料
| 型号： | X4325V8I-2.7A |
| 厂商： | INTERSIL CORP |
| 元件分类： | 电源管理 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封装： | 4.40 MM, PLASTIC, MO-153AC, TSSOP-8 |
| 文件页数： | 15/21页 |
| 文件大小： | 333K |
| 代理商： | X4325V8I-2.7A |
15
FN8122.0
March 29, 2005
CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V)
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
A.C. CHARACTERISTICS
(Over recommended operating conditions, unless otherwise specified)
Notes: (1) Typical values are for T
A
= 25°C and V
CC
= 5.0V
(2) Cb = total capacitance of one bus line in pF.
Symbol
C
OUT
(4)
C
IN
(4)
Parameter
Max.
8
6
Units
pF
pF
Test Conditions
V
OUT
= 0V
V
IN
= 0V
Output Capacitance (SDA, RST/RST)
Input Capacitance (SCL, WP)
1533
100pF
5V
For V
OL
= 0.4V
and I
OL
= 3 mA
SDA
or
RESET
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
0.1V
CC
to 0.9V
CC
10ns
0.5V
CC
Standard output load
Symbol
f
SCL
t
IN
t
AA
t
BUF
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
DH
t
R
t
F
t
SU:WP
t
HD:WP
Cb
Parameter
Min.
0
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb
20 +.1Cb
0.6
0
Max.
400
Unit
kHz
ns
μs
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
μs
μs
pF
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
WP Hold Time
Capacitive load for each bus line
0.9
300
300
400
X4323, X4325
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