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参数资料
| 型号： | X4325V8I |
| 厂商： | INTERSIL CORP |
| 元件分类： | 电源管理 |
| 英文描述： | CABLE ASSEMBLY; LEAD-FREE SOLDER; TNC MALE TO TNC MALE; 50 OHM, RG58C/U COAX; 12" CABLE LENGTH; *USES STANDARD 50 OHM INTERFACE CONNECTORS* |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封装： | 4.40 MM, PLASTIC, MO-153AC, TSSOP-8 |
| 文件页数： | 13/21页 |
| 文件大小： | 333K |
| 代理商： | X4325V8I |
13
FN8122.0
March 29, 2005
Figure 15. X4323/5 Addressing
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– RESET Signal is active for t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, and WPEN bit at logic
HIGH will prevent all writes to the Control Register.
– Communication to the device is inhibited while
RESET/RESET is active and any in-progress com-
munication is terminated.
– Block Lock bits can protect sections of the memory
array from write operations.
SYMBOL TABLE
R/W
S0
S1
0
0
1
0
1
Slave Address Byte
Device Identifier
Device Select
A8
(X2)
A9
(X3)
A10
(X4)
A11
(X5)
0
0
0
0
Word Address Byte 0–32K
High Order Word Address
A0
(Y0)
A1
(Y1)
A2
(Y2)
Word Address Byte 0 for all options
Low Order Word Address
A3
(Y3)
A4
(Y4)
A5
(Y5)
A6
(X0)
A7
(X1)
D0
D1
D2
D3
D4
D5
D6
D7
Data Byte for all options
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
X4323, X4325
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