参数资料
| 型号： | X4645V8I-4.5A |
| 厂商： | Intersil |
| 文件页数： | 13/21页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU 64K EE 8-TSSOP |
| 标准包装： | 100 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 复位： | 高有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 4.62V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 管件 |
X4643, X4645
Figure 15. X4643/5 Addressing
Device Identifier
Device Select
1
0
1
0
0
S1
S0
R/W
Slave Address Byte
High Order Word Address
0
0
0
A12
(X6)
A11
(X5)
A10
(X4)
A9
(X3)
A8
(X2)
Word Address Byte 0–64K
Low Order Word Address
A7
(X1)
A6
(X0)
A5
(Y5)
A4
(Y4)
A3
(Y3)
A2
(Y2)
A1
(Y1)
A0
(Y0)
Word Address Byte 0 for all options
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte for all options
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– Communication to the device is inhibited while
RESET/RESET is active and any in-progress com-
munication is terminated.
– Block Lock bits can protect sections of the memory
array from write operations.
SYMBOL TABLE
– RESET/RESET Signal is active for t PURST .
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
block lock settings.
– The WP pin, when held HIGH, and WPEN bit at logic
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
HIGH will prevent all writes to the Control Register.
13
FN8123.0
March 29, 2005
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