参数资料
型号: X5001P-2.7A
厂商: Intersil
文件页数: 1/20页
文件大小: 0K
描述: IC SUPERVISOR CPU 8-DIP
标准包装: 50
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 100 ms
电压 - 阀值: 2.92V
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
?
X5001
Data Sheet
May 30, 2006
FN8125.1
CPU Supervisor
FEATURES
? 200ms power-on reset delay
? Low V CC detection and reset assertion
—Five standard reset threshold voltages
—Adjust low V CC reset threshold voltage using
special programming sequence
—Reset signal valid to V CC = 1V
? Selectable nonvolatile watchdog timer
—0.2, 0.6, 1.4 seconds
—Off selection
—Select settings through software
? Long battery life with low power consumption
—<50μA max standby current, watchdog on
—<1μA max standby current, watchdog off
? 2.7V to 5.5V operation
? SPI mode 0 interface
? Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Watchdog change latch
? High reliability
? Available packages
—8 Ld TSSOP
—8 Ld SOIC
—8 Ld PDIP
? Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
DESCRIPTION
This device combines three popular functions, Power-
on Reset, Watchdog Timer, and Supply Voltage
Supervision in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
The watchdog timer provides an independent protec-
tion mechanism for microcontrollers. During a system
failure, the device will respond with a RESET signal
after a selectable time out interval. The user selects the
interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The user’s system is protected from low voltage condi-
tions by the device’s low V CC detection circuitry. When
V CC falls below the minimum V CC trip point, the system
is reset. RESET is asserted until V CC returns to proper
operating levels and stabilizes. Five industry standard
V TRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
The device utilizes Intersil’s proprietary Direct Write ?
cell for the watchdog timer control bits and the V TRIP
storage element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.
SI
Data
Watchdog
Transition
Detector
Watchdog
Timer
RESET
SO
SCK
CS/WDI
V CC
Register
Command
Decode &
Control
Logic
+
Reset &
Watchdog
Timebase
Power-on/
Low Voltage
REset
Generation
1
V TRIP
-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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