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参数资料
| 型号： | X5083V8IZ-2.7 |
| 厂商： | Intersil |
| 文件页数： | 10/21页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU 8K EE 8-TSSOP |
| 标准包装： | 100 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 复位： | 低有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 2.63V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 管件 |
X5083
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
? A WREN instruction must be issued to set the write enable
latch.
? CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
? When V CC is below V TRIP , communications to the device
are inhibited.
CS
0
1
2
3
4
5
6
7
8
9
2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0
SCK
SI
Read Instruction
(1 Byte)
Byte Address (2 Byte)
15 14 3 2
1
0
Data Out
SO
High Impedance
7
6
5
4
3
2
1
0
FIGURE 5. READ OPERATION SEQUENCE
CS
SCK
0
1
2
3
4
5
6
7
...
SI
Read Status
Instruction
...
SO
W
D
1
W
D
0
B
L
2
B
L
1
B
L
0
...
SO = Status Reg When no Nonvolatile
Write Cycle
FIGURE 6. READ STATUS OPERATION SEQUENCE
10
FN8127.3
June 15, 2006
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相关代理商/技术参数 |
参数描述 |
|---|---|
| X5083V8IZ-4.5A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CPU Supervisor with 8Kbit SPI EEPROM |
| X5083V8Z | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CPU Supervisor with 8Kbit SPI EEPROM |
| X5083V8Z-2.7 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CPU Supervisor with 8Kbit SPI EEPROM |
| X5083V8Z-2.7A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CPU Supervisor with 8Kbit SPI EEPROM |
| X5083V8Z-4.5A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CPU Supervisor with 8Kbit SPI EEPROM |
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